Patents by Inventor Tao-Cheng Liu

Tao-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110274
    Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a first top oxide layer and a silicon layer that is formed on the first top oxide layer. The structure further includes a plurality of rib waveguide components that are formed in the silicon layer. A first rib waveguide component of the plurality includes first contact holes having a first contact hole depth, and a second rib waveguide component of the plurality includes second contact holes having a second contact hole depth, such that the depths of the first contact hole and the second contact hole are different.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Shih-Yu Liao, Tao-Cheng Liu
  • Publication number: 20240361549
    Abstract: A photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: TAO-CHENG LIU, YING-HSUN CHEN
  • Publication number: 20240359969
    Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen, Chen-Hsuan Yen
  • Patent number: 12122665
    Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tao-Cheng Liu, Chen-Hsuan Yen, Ying-Hsun Chen
  • Publication number: 20240332350
    Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.
    Type: Application
    Filed: June 5, 2024
    Publication date: October 3, 2024
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen
  • Publication number: 20240302591
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
  • Patent number: 12078856
    Abstract: A photonic structure is provided. The photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen
  • Patent number: 12040353
    Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen
  • Patent number: 12013570
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20240063251
    Abstract: A semiconductor device includes a substrate, a first multilayer capacitor, and a second multilayer capacitor. The first multilayer capacitor includes a first plurality of conductive layers. The semiconductor device further includes a first set of contacts including a first contact electrically connected to a first conductive layer, and a second contact electrically connected to a second conductive layer, wherein the first contact is spaced from the second contact by a first distance. The second multilayer capacitor includes a second plurality of conductive layers. The semiconductor device further includes a second set of contacts including a third contact electrically connected to a third conductive layer, and a fourth contact electrically connected to a fourth conductive layer, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
  • Patent number: 11810945
    Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
  • Publication number: 20230326979
    Abstract: A semiconductor device and method of forming the semiconductor device are disclosed. The method includes forming first and second conductive structures on a semiconductor substrate, forming one or more dielectric layers between the first and second conductive structures, covering the one or more dielectric layers with a first masking layer, forming a first opening in the first masking layer, depositing a conductive material in the first opening to form a field plate structure, and electrically connecting the field plate structure to another conductor.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen
  • Patent number: 11688754
    Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen
  • Publication number: 20230152521
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 18, 2023
    Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
  • Publication number: 20230066352
    Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Tao-Cheng Liu, Ying-Hsun Chen
  • Publication number: 20230066841
    Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Tao-Cheng LIU, Chen-Hsuan YEN, Ying-Hsun CHEN
  • Patent number: 11585982
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20230043634
    Abstract: A photonic structure is provided. The photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 9, 2023
    Inventors: TAO-CHENG LIU, YING-HSUN CHEN
  • Publication number: 20220392945
    Abstract: A method is provided that includes forming a cavity in a substrate. The cavity is formed to extend into the substrate from a first surface to a second surface. Sidewall spacers are formed on sidewalls of the substrate in the cavity. A semiconductor layer is formed on the second surface in the cavity of the substrate, and the semiconductor layer abuts the sidewall spacers in the cavity.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen
  • Publication number: 20220310520
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE