Patents by Inventor Tao-Cheng Liu
Tao-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063251Abstract: A semiconductor device includes a substrate, a first multilayer capacitor, and a second multilayer capacitor. The first multilayer capacitor includes a first plurality of conductive layers. The semiconductor device further includes a first set of contacts including a first contact electrically connected to a first conductive layer, and a second contact electrically connected to a second conductive layer, wherein the first contact is spaced from the second contact by a first distance. The second multilayer capacitor includes a second plurality of conductive layers. The semiconductor device further includes a second set of contacts including a third contact electrically connected to a third conductive layer, and a fourth contact electrically connected to a fourth conductive layer, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
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Patent number: 11810945Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.Type: GrantFiled: December 9, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
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Publication number: 20230326979Abstract: A semiconductor device and method of forming the semiconductor device are disclosed. The method includes forming first and second conductive structures on a semiconductor substrate, forming one or more dielectric layers between the first and second conductive structures, covering the one or more dielectric layers with a first masking layer, forming a first opening in the first masking layer, depositing a conductive material in the first opening to form a field plate structure, and electrically connecting the field plate structure to another conductor.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Inventors: Tao-Cheng Liu, Ying-Hsun Chen
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Patent number: 11688754Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.Type: GrantFiled: May 6, 2020Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen
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Publication number: 20230152521Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.Type: ApplicationFiled: January 9, 2023Publication date: May 18, 2023Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
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Publication number: 20230066352Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Tao-Cheng Liu, Ying-Hsun Chen
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MICRO-ELECTROMECHANICAL SYSTEM DEVICE USING A METALLIC MOVABLE PART AND METHODS FOR FORMING THE SAME
Publication number: 20230066841Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Tao-Cheng LIU, Chen-Hsuan YEN, Ying-Hsun CHEN -
Patent number: 11585982Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.Type: GrantFiled: February 22, 2021Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
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Publication number: 20230043634Abstract: A photonic structure is provided. The photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.Type: ApplicationFiled: February 15, 2022Publication date: February 9, 2023Inventors: TAO-CHENG LIU, YING-HSUN CHEN
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Publication number: 20220392945Abstract: A method is provided that includes forming a cavity in a substrate. The cavity is formed to extend into the substrate from a first surface to a second surface. Sidewall spacers are formed on sidewalls of the substrate in the cavity. A semiconductor layer is formed on the second surface in the cavity of the substrate, and the semiconductor layer abuts the sidewall spacers in the cavity.Type: ApplicationFiled: August 9, 2022Publication date: December 8, 2022Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen
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Publication number: 20220310520Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE
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Patent number: 11373952Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: GrantFiled: October 8, 2020Date of Patent: June 28, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Chiang Kuo, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
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Patent number: 11227958Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.Type: GrantFiled: April 30, 2020Date of Patent: January 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Ying-Hsun Chen
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Publication number: 20210351221Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.Type: ApplicationFiled: May 6, 2020Publication date: November 11, 2021Inventors: Tsai-Hao HUNG, Tao-Cheng LIU, Ying-Hsun CHEN
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Publication number: 20210343883Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.Type: ApplicationFiled: April 30, 2020Publication date: November 4, 2021Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Ying-Hsun CHEN
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Publication number: 20210199889Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.Type: ApplicationFiled: February 22, 2021Publication date: July 1, 2021Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
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Publication number: 20210118978Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.Type: ApplicationFiled: December 9, 2020Publication date: April 22, 2021Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
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Patent number: 10928590Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.Type: GrantFiled: April 23, 2020Date of Patent: February 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
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Publication number: 20210028118Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: ApplicationFiled: October 8, 2020Publication date: January 28, 2021Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE
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Patent number: 10868107Abstract: Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.Type: GrantFiled: June 20, 2017Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee