Patents by Inventor Tao-Cheng Liu

Tao-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230043634
    Abstract: A photonic structure is provided. The photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 9, 2023
    Inventors: TAO-CHENG LIU, YING-HSUN CHEN
  • Publication number: 20220392945
    Abstract: A method is provided that includes forming a cavity in a substrate. The cavity is formed to extend into the substrate from a first surface to a second surface. Sidewall spacers are formed on sidewalls of the substrate in the cavity. A semiconductor layer is formed on the second surface in the cavity of the substrate, and the semiconductor layer abuts the sidewall spacers in the cavity.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Tsai-Hao Hung, Tao-Cheng Liu, Ying-Hsun Chen
  • Publication number: 20220310520
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE
  • Patent number: 11373952
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Chiang Kuo, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
  • Patent number: 11227958
    Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Ying-Hsun Chen
  • Publication number: 20210351221
    Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.
    Type: Application
    Filed: May 6, 2020
    Publication date: November 11, 2021
    Inventors: Tsai-Hao HUNG, Tao-Cheng LIU, Ying-Hsun CHEN
  • Publication number: 20210343883
    Abstract: An integrated circuit includes a photodetector. The photodetector includes a circular optical grating formed in an annular trench in a semiconductor substrate. The circular optical grating includes dielectric fins and photosensitive fins positioned in the annular trench. The circular optical grating is configured to receive incident light and to direct the incident light around the annular trench through the dielectric fins and the photosensitive fins until the light is absorbed by one of the photosensitive fins.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Ying-Hsun CHEN
  • Publication number: 20210199889
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 1, 2021
    Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
  • Publication number: 20210118978
    Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.
    Type: Application
    Filed: December 9, 2020
    Publication date: April 22, 2021
    Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
  • Patent number: 10928590
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20210028118
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE
  • Patent number: 10868107
    Abstract: Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
  • Patent number: 10804206
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Chiang Kuo, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
  • Publication number: 20200249397
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
  • Patent number: 10641958
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Patent number: 10508020
    Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Hao Hung, Shih-Chi Kuo, Tsung-Hsien Lee, Tao-Cheng Liu
  • Publication number: 20190293867
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: April 8, 2019
    Publication date: September 26, 2019
    Inventors: Tao-Cheng LIU, Tsai-Hao Hung, Shih-Chi Kuo
  • Patent number: 10274678
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20190035736
    Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
    Type: Application
    Filed: February 23, 2018
    Publication date: January 31, 2019
    Inventors: Fu-Chiang KUO, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
  • Publication number: 20180366537
    Abstract: Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE