Patents by Inventor Tao Chu
Tao Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7483083Abstract: A method for enhancing video or other multimedia in order to achieve a closer-to-movie theater viewing experience. The enhancement method can be applied to YUV or other video formats which are used for TV or digital media. The method provides a curve with at least one inflection point such that at least one region has a concave upward arc and another region has a concave downward arc. The improved curve provides relatively less contrast in relatively dark regions and relatively more contrast in relatively bright regions. By taking into account the visual sensitivity to various luminance levels, a neutral point is selected to be located at a relatively dark point. To the darker side of the neutral point, luminance is suppressed. To the brighter side of the neutral point, luminance is enhanced. This luminance-mapping curve is applied to the luminance (Y) signal so as to enhance both brightness and contrast.Type: GrantFiled: April 13, 2004Date of Patent: January 27, 2009Assignee: Intervideo, Inc.Inventors: Wei Li, Chung-Tao Chu, Andy Chao Hung
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Publication number: 20080107184Abstract: A method and an apparatus for performing multi-threaded video decoding are disclosed. The method takes use of a multi-threaded scheme to process an encoded picture stream on a picture by picture basis. In the method, multiple threads are used for performing video decoding at the same time, such as one thread for the operation of parsing input bits into syntax elements of one picture implemented by the first thread, another thread for the operation of decoding the parsed syntax elements of another picture into pixel values implemented by the second thread, and the other threads for the operations of the non-reference picture, such as bidirectional predictive picture, including parsing input bits into syntax elements and the subsequent operation of decoding the parsed syntax elements into pixel values. Therefore, the decoding speed is substantially increased, and the decoding efficiency is enhanced.Type: ApplicationFiled: November 2, 2006Publication date: May 8, 2008Applicant: INTERVIDEO, INC.Inventors: Ioannis Katsavounidis, Yu-Nien Chien, Chun-Huan Chuang, Chung-Tao Chu, Te-Chien Chen
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Publication number: 20060067698Abstract: The present invention is an optical fiber system and method for carrying both CATV and Ethernet signals. The digital signals are translated into higher band by a direct up/down conversion so that analog signals and digital signals are treated as different frequency bands of electrical signals. Then, all the signals are mixed/divided by a power combiner/divider. And then, by using optoelectronic devices, the signals are processed with optoelectronic conversion. The converted optical signals are transmitted in a fiber or a related optical channel having low channel loss yet high capacity. To sum up, the present invention can transmit digital signals together with analog signals in a single wavelength to save the cost of an optical signal system and to provide a convenience on rearranging the system.Type: ApplicationFiled: September 24, 2004Publication date: March 30, 2006Inventors: Yi-Jen Chan, Fan-Hsiu Huang, Hsin-Pin Wang, Dong-Min Lin, Mu-Tao Chu, Shin-Ge Lee, Shun-Tien Lee
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Patent number: 6850566Abstract: A system for improving the speed of the video encoding process by decreasing the number of cycles to perform the quantization. The disclosed system achieves the improvement through use of parallel processor such as one having a Single Instruction, Multiple Data (SIMD) architecture. Concurrent processing during one instruction cycle is accomplished, thereby leading overall to the use of fewer instruction cycles. In the preferred embodiment, an MMX instruction set is used for executing four quantization in parallel. The disclosed system also achieves a higher precision of the quantization during the encoding of video signals with the SIMD architecture by using a larger multiplier and larger shift factor.Type: GrantFiled: February 20, 2001Date of Patent: February 1, 2005Assignee: InterVideo, Inc.Inventors: Chung-Tao Chu, Wei Ding
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Publication number: 20040207759Abstract: A method for enhancing video or other multimedia in order to achieve a closer-to-movie theater viewing experience. The enhancement method can be applied to YUV or other video formats which are used for TV or digital media. The method provides a curve with at least one inflection point such that at least one region has a concave upward arc and another region has a concave downward arc. The improved curve provides relatively less contrast in relatively dark regions and relatively more contrast in relatively bright regions. By taking into account the visual sensitivity to various luminance levels, a neutral point is selected to be located at a relatively dark point. To the darker side of the neutral point, luminance is suppressed. To the brighter side of the neutral point, luminance is enhanced. This luminance-mapping curve is applied to the luminance (Y) signal so as to enhance both brightness and contrast.Type: ApplicationFiled: April 13, 2004Publication date: October 21, 2004Inventors: Wei Li, Chung-Tao Chu, Andy Chao Hung
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Patent number: 6743735Abstract: Removing photoresist from alignment marks on a semiconductor wafer using a wafer edge exposure process is disclosed. The alignment marks on the wafer are covered by photoresist used in conjunction with semiconductor processing of one or more layers deposited on the semiconductor wafer. One or more parts of the edge of the wafer are exposed to remove the photoresist from these parts and thus reveal alignment marks on the wafer. The exposure of the one or more parts of the wafer is accomplished without performing a photolithographic clear out process. Rather, a wafer edge exposure (WEE) process is inventively utilized. Once the WEE process is performed, subsequent layers may be deposited by aligning them using the revealed alignment marks.Type: GrantFiled: March 19, 2002Date of Patent: June 1, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Po-Tao Chu, Hsin-Yuan Chen, Chung-Jen Chen, Tai-Ming Yang, Cheng-Ming Wu
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Publication number: 20030181058Abstract: Removing photoresist from alignment marks on a semiconductor wafer using a wafer edge exposure process is disclosed. The alignment marks on the wafer are covered by photoresist used in conjunction with semiconductor processing of one or more layers deposited on the semiconductor wafer. One or more parts of the edge of the wafer are exposed to remove the photoresist from these parts and thus reveal alignment marks on the wafer. The exposure of the one or more parts of the wafer is accomplished without performing a photolithographic clear out process. Rather, a wafer edge exposure (WEE) process is inventively utilized. Once the WEE process is performed, subsequent layers may be deposited by aligning them using the revealed alignment marks.Type: ApplicationFiled: March 19, 2002Publication date: September 25, 2003Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Po-Tao Chu, Hsin-Yuan Chen, Chung-Jen Chen, Tai-Ming Yang, Cheng-Ming Wu
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Publication number: 20030067977Abstract: A system for improving the speed of the video encoding process by decreasing the number of cycles to perform the quantization. The disclosed system achieves the improvement through use of a parallel processor, such as one having a Single Instruction, Multiple Data (SIMD) architecture. Concurrent processing during one instruction cycle is accomplished, thereby leading overall to the use of fewer instruction cycles. In a preferred embodiment of the invention, an MMX instruction is used for executing four quantizations in parallel. The disclosed system also achieves a higher precision of the quantization during the encoding of video signals (60) with the SIMD architecture by using a larger multiplier and larger shift factor (50).Type: ApplicationFiled: September 18, 2001Publication date: April 10, 2003Inventors: Chung-Tao Chu, Wei Ding
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Patent number: 6511235Abstract: The present invention pertains to an integrated surface-emitting optoelectronic module and the method for making the same. The yellow light procedure is performed to define a V-groove width for disposing an optical fiber on a silicon substrate. After dry etching a vertical groove, a dielectric layer is grown on the surface of the silicon substrate to protect the vertical wall, preventing the groove from getting wider due to subsequent wet etching. A 45-degree mirror surface is formed so that an optoelectronic device can be disposed on the mirror surface in the flip chip method. The optoelectronic module employs a complete silicon substrate to assemble a surface-emitting optoelectronic devices and an optical fiber by passive alignment, and therefore can be free from misalignment due to separate assembly.Type: GrantFiled: December 19, 2000Date of Patent: January 28, 2003Assignee: Industrial Technology Research InstituteInventors: Weng-Jin Wu, Yih-Der Guo, Tsung-Hsuan Chiu, Rong-Heng Yuang, Mu-Tao Chu
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Patent number: 6483864Abstract: A partial reflective laser output device comprising a partial reflective unit mounted on a laser output device (such as a vertical cavity emitting laser), the partial reflective unit allowing the laser beam emitted from the laser output device to be partially reflected while the rest penetrating through. On one hand, this device decreases the intensity of output laser light so as to comply with the eye safety standard; the reflected light is absorbed by a photodiode (PD) to perform auto power control on the laser output device on the other. In addition, by adjusting the tilting angle of the partial reflective unit or making a curvature thereon, the reflected light can have no destructive interference with the output light and can even be focused onto the PD so that there would be no relative intensity noise problem and the size of the PD can be made smaller to lower the cost.Type: GrantFiled: April 20, 2000Date of Patent: November 19, 2002Assignee: Industrial Technology Research InstituteInventors: Rong-Heng Yuang, Chia-Ming Tsai, Ding-Wei Huang, Mu-Tao Chu
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Publication number: 20020037137Abstract: The present invention pertains to an integrated surface-emitting optoelectronic module and the method for making the same. The yellow light procedure is performed to define a V-groove width for disposing an optical fiber on a silicon substrate. After dry etching a vertical groove, a dielectric layer is grown on the surface of the silicon substrate to protect the vertical wall, preventing the groove from getting wider due to subsequent wet etching. A 45-degree mirror surface is formed so that an optoelectronic device can be disposed on the mirror surface in the flip chip method. The optoelectronic module employs a complete silicon substrate to assemble a surface-emitting optoelectronic devices and an optical fiber by passive alignment, and therefore can be free from misalignment due to separate assembly.Type: ApplicationFiled: December 19, 2000Publication date: March 28, 2002Inventors: Wing-Jin Wu, Yih-Der Guo, Tsung-Hsuan Chiu, Rong-Heng Yuang, Mu-Tao Chu
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Patent number: 6320987Abstract: An apparatus for processing a video signal is described, comprising a means for receiving a nonreconstructed, video residue image, a means for selecting a first pixel to be processed, a means for selecting a second and third pixel, the second and third pixels being contiguous to said first pixel, and positioned right and left of the first pixel, a means for determining first, second, and third weighting factors for the first, second and third pixels respectively, a means for computing a first result by multiplying the first weighting factor with the value of said first pixel, a means for computing a second result by multiplying the second weighting factor with the value of the second pixel, a means for computing a third result by multiplying the third weighting factor with the value of the third pixel; and a means for computing a new value for said first pixel by adding the first, second and third results together.Type: GrantFiled: October 16, 1998Date of Patent: November 20, 2001Assignee: Neo Paradigm Labs, Inc.Inventor: Chung-Tao Chu
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Patent number: 6077776Abstract: A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.Type: GrantFiled: March 18, 1998Date of Patent: June 20, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ching-Wen Cho, Cheng-Fu Hsu, Sen-Fu Chen, Po-Tao Chu
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Patent number: 6051505Abstract: A plasma etch method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a plasma reactor chamber. There is then fixed within the plasma reactor chamber a microelectronics fabrication. The microelectronics fabrication comprises: (1) a substrate employed within the microelectronics fabrication; (2) a metal layer formed over the substrate; (3) a silicon containing dielectric layer formed upon the metal layer; and (4) a patterned photoresist layer formed upon the silicon containing dielectric layer. There is then etched through use of a plasma etch method at a first plasma reactor chamber pressure while employing the patterned photoresist layer as a photoresist etch mask layer the silicon containing dielectric layer to form a patterned silicon containing dielectric layer while reaching and etching the metal layer to form an etched metal layer.Type: GrantFiled: March 5, 1998Date of Patent: April 18, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Po-Tao Chu, Ming-Chieh Yeh, Fang-Cheng Chen, Ting-Yih Lu
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Patent number: 6006764Abstract: The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.Type: GrantFiled: January 28, 1997Date of Patent: December 28, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Tao Chu, Ching-Wen Cho, Chia-Hung Lai, Chih-Chien Hung
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Patent number: 5746928Abstract: A method of cleaning an electrostatic chuck of a plasma etching apparatus wherein a dummy wafer is placed on the chuck, the chamber evacuated, and an RF voltage applied that is greater than the normal RF voltage used to etch.Type: GrantFiled: June 3, 1996Date of Patent: May 5, 1998Assignee: Taiwan Semiconductor Manufacturing Company LtdInventors: Shih Kuei Yen, Po-Tao Chu, Kuang-Hui Chang
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Patent number: 5672543Abstract: A new method of metallization using a tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer covers the semiconductor device structures wherein a contact opening is made through the insulating layer to the semiconductor substrate. A barrier layer is deposited conformally over the surface of the insulating layer and within the contact opening. A stress buffer layer is deposited overlying the barrier layer wherein the stress buffer layer prevents volcano defects. A tungsten plug is formed within the contact opening to complete the formation of the tungsten plug metallization without volcano defects in the fabrication of an integrated circuit device.Type: GrantFiled: April 29, 1996Date of Patent: September 30, 1997Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaur Rong Chang, Po-Tao Chu, Tzu-Min Peng, Kuang-Hui Chang
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Patent number: 5604134Abstract: Plasma reactors are used extensively in the manufacture of integrated circuits for the deposition and etching of thin films at low temperatures. Their range of operating temperatures and gas pressures make them highly susceptible to build-up of deposits on the inner surfaces of the reaction chamber which subsequently become dislodged by vibrations, stresses, and other aggravations and are dispersed within the system as particulates. The monitoring of particulate accumulation on wafers is conventionally done by subjecting a test wafer to a simulated operation within the tool under gas flow alone. Some types of plasma reactors incorporate oscillating gas dispersion housings in order to improve homogeneity of the gas mixture. The motion of these housings can induce significant particle displacement within the chamber. The correct monitoring procedure for these tools must therefore include the motion of the distribution housing in addition to the conventional procedures.Type: GrantFiled: February 2, 1996Date of Patent: February 18, 1997Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Hui Chang, Tzu-Min Peng, Po-Tao Chu, Shin-Kuei Yen
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Patent number: 5554563Abstract: A process for preventing the formation of precipitates on a substrate surface containing titanium after a contact layer (e.g., tungsten layer) etch back. The process involves removing the precursor chemicals of the precipitate. With the invention, the precursor are removed by baking the substrate at a temperature of approximately 120.degree. C. for approximately 80 seconds. Preferably, the baking process is performed in situ by a halogen lamp mounted on the exit loading dock of the etcher thereby not impacting the wafer throughput of the etcher.Type: GrantFiled: April 4, 1995Date of Patent: September 10, 1996Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Po-Tao Chu, Kuang-Hui Chang, Yuan-Chang Huang
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Patent number: D579456Type: GrantFiled: September 28, 2007Date of Patent: October 28, 2008Assignees: Industrial Technology Research InstituteInventors: Chen-Kun Chen, Yu-Chen Yu, Mu-Tao Chu, Chao-Chin Chang