Abstract: Described herein are compounds that activate pyruvate kinase, pharmaceutical compositions and methods of use thereof. These compounds are represented by Formula (I) wherein R1, R2, Ra, Rb, Rj, Rk, and Q are as defined herein.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.

Abstract: The present disclosure provides an etching defect detection method, relating to the field of semiconductor technology. The detection method includes: providing a substrate, and sequentially forming a conductive layer and a dielectric layer on the substrate; etching the dielectric layer to form a trench structure; taking the conductive layer as a cathode, and filling the trench structure with an electroplating layer by an electroplating process, to form a product to-be-detected; and testing the product to-be-detected by a defect density detection assembly, to obtain a top-view image of the trench structure, and determining an etching defect of the product to-be-detected according to the top-view image. The etching defect detection method can improve the accuracy of defect identification and prevent a capacitor from failing due to suspension.

Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

Abstract: The invention relates to a poly(butylene terephthalate) (PBT)-based composition, comprising a) PBT, and b) another thermoplastic polymer from the group consisting of polypropylene (PP), and/or at least one polyester which is selected from the group consisting of liquid crystal polyester (LCP), poly(ethylene terephthalate) (PET) including low melting point polyester, poly(butylene naphthalate) (PBN) and poly(ethylene naphthalate) (PEN), to a method for preparing the PBT-based composition, to a use of the PBT-based composition according to the invention in increasing electrolyte resistance, in particular in battery applications, especially in Li-ion batteries, and to an article obtained from the PBT-based composition according to the invention.

Abstract: A text to speech processing method implemented by a terminal includes detecting an instruction to perform a text to speech conversion, sending text to a server downloading from the server, audio data based on the text, determining whether a first frame of playable audio data is downloaded within a preset duration, and continuing to download remaining audio data when the first frame is downloaded within the preset duration.

Abstract: An automatic recognition and classification method for electrocardiogram heartbeat based on artificial intelligence, comprising: processing a received original electrocardiogram digital signal to obtain heartbeat time sequence data and lead heartbeat data; cutting the lead heartbeat data according to the heartbeat time sequence data to generate lead heartbeat analysis data; performing data combination on the lead heartbeat analysis data to obtain a one-dimensional heartbeat analysis array; performing data dimension amplification and conversion according to the one-dimensional heartbeat analysis array to obtain four-dimensional tensor data; and inputting the four-dimensional tensor data to a trained LepuEcgCatNet heartbeat classification model, to obtain heartbeat classification information.

Abstract: A method for preparing an electron donor biofilm carrier includes proportioning organic polymer basic raw material and functional modifiers in a range of set-point, mixing the materials, feeding the mixtures into a screw extruder, processing them into a bar-type material, and then cut the bar-type material into granules with the cutting machine, and feeding the granules into the screw extruder, processing them into pipes of various shapes according to the selected screw extruder heads, and then cutting the pipes according to the required size. The electron donor biofilm carrier is mainly used in anaerobic or anoxic suspended carrier biofilm technologies. Electron donors with a standard electrode potential below 100 Mv are used as the functional material for preparation of electron donor biofilm carrier.

Abstract: An optical communication device includes two optical transmitting devices, two optical receiving devices, an optical path component, and an optical fiber adapter. A first converging lens packaged in each of the optical transmitting devices converges a light beam emitted by a light source, and provides the converged light beam for the optical path component. A second converging lens packaged in each of the optical receiving devices converges a light beam from the optical path component, and provides the converged light beam for a photoelectric detection element. The optical path of the optical communication device is simplified and the process costs are reduced. In addition, the quantity of used lenses is reduced, correspondingly reducing the quantity of optical coupling dimensions between mechanical parts and improving production efficiency of combined passive optical network (Combo PON) products.

Abstract: A light control film comprises a light input surface and a light output surface; alternating transmissive regions and absorptive regions disposed between the light input surface and the light output surface; and TIR cladding layers. The TIR cladding layer having a refractive index, nTIR. The transmissive regions alternate between high refractive index transmissive regions having a refractive index, n2, and low refractive index transmissive regions having a refractive index, n1. The absorptive regions comprise a core having a refractive index, ncore, adjacent an AR cladding layer; wherein n1<n2 and nTIR<n2. The TIR cladding layers are adjacent the high refractive index transmissive regions. The cores have an aspect ratio of at least 20. The high refractive index transmissive regions have a wall angle of 6 degrees or less.

Abstract: A target recognition method includes performing first image processing on first image data, to obtain first artificial intelligence (AI) input data; performing second image processing on second image data, to obtain second AI input data, where exposure duration corresponding to the first AI input data is different from exposure duration corresponding to the second AI input data, or a dynamic range corresponding to the first AI input data is different from a dynamic range corresponding to the second AI input data, and both the first image data and the second image data are raw image data generated by an image sensor; and performing target recognition based on the first AI input data and the second AI input data, and determining target information.

Abstract: Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: The present application relates to a mask structure, a semiconductor structure and methods for manufacturing the same. The method for manufacturing a mask structure includes: dividing an overall structure into two regions, and developing the array region and the periphery region with a negative photoresist.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: Turn-off circuits. In one aspect, the turn-off circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, a first pull-down circuit connected to the gate terminal, a second pull-down circuit connected to the gate terminal, and a third pull-down circuit connected to the gate terminal. In another aspect, the first, the second and the third pull-down circuits are arranged to cause a turn off of the transistor by changing a voltage at the gate terminal at a first rate of voltage with respect to time from an on-state voltage to a first intermediate voltage, and from the first intermediate voltage to a second intermediate voltage at a second rate of voltage with respect to time, and from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time, wherein the first rate is higher than the second rate.

Abstract: A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A high-voltage hierarchy hundred-megawatt level (100 MW) battery energy storage system and optimizing and control methods are provided. The system includes a multi-phase structure, of which each phase is divided into multi-story spaces from top to bottom. A battery module is provided in each story of the multi-story spaces. The battery module is connected to a DC terminal of an H-bridge converter, and each phase is cascaded by the H-bridge converter. A capacity of the single-phase energy storage apparatus of the present invention is large, and multiple phases can be connected in parallel to form a 100 MW battery energy storage power station. The power station has the advantages of simple structure, easy coordinated control, low control loop model and coupling, and optimal system stability. The control system of the present invention has fewer hierarchies, a small information transmission delay, and a rapid response speed.