Abstract: System and methods are provided for touch detection. The system includes: a sensing capacitive network configured to generate a touch-sensing signal based at least in part on a touch panel capacitance; an internal capacitive network configured to generate an input signal based at least in part on a predetermined internal capacitance; a comparative network configured to compare the touch-sensing signal with a reference signal to generate a first comparison result and compare the input signal with the reference signal to generate a second comparison result; and a signal processing component configured to generate a detection result to indicate ether a touch event occurs on the touch panel based at least in part on the first comparison result and the second comparison result.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a signal amplifying circuit coupled with a crystal component of a natural frequency to form a crystal oscillator, and a signal generator circuit configured to generate a signal with an energy distribution about the natural frequency, and to provide the signal to the crystal oscillator to assist the crystal oscillator to begin oscillating.

Abstract: In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved.

Abstract: New and highly stable oscillators are disclosed.

Abstract: A beta enhancement circuit includes a current source connected in series with a transistor between two voltage supply lines. In an embodiment, the voltage supply lines are configured for connection to a power source and ground potential. A resistor device is connected between a control terminal of the transistor device and one of voltage supply lines. A value for the resistor device is selected based on one or more process dependent parameters of the transistor.

Abstract: A resonant element driver circuit includes a NMOS transistor and a PMOS transistor that are configured to drive a resonant element. The resonant element driver circuit includes biasing circuitry that is configured to bias the PMOS transistor. The biasing circuitry receives a reference signal that is used to set the biasing on the PMOS transistor. The resonant element driver further includes mirror circuitry that tracks current flowing through the NMOS and PMOS transistors.

Abstract: An oscillator includes a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator.

Abstract: Aspects of the disclosure process an amplifier circuit. The amplifier circuit includes an input stage, an intermediate stage, an output stage and a detecting and controlling circuit. The input stage is configured to receive an electrical signal for amplification. The intermediate stage is configured to amplify with an adjustable gain. The output stage is configured to drive an audio output device in response to the amplified electrical signal. The detecting and controlling circuit is configured to detect a current for driving the audio output device, and adjust the gain of the intermediate stage based on the current to compensate for a pole change of the amplifier circuit due to a change of the current.

Abstract: A beta enhancement circuit includes a current source connected in series with a transistor between two voltage supply lines. In an embodiment, the voltage supply lines are configured for connection to a power source and ground potential. A resistor device is connected between a control terminal of the transistor device and one of voltage supply lines. A value for the resistor device is selected based on one or more process dependent parameters of the transistor.

Abstract: In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved.

Abstract: In accordance with the teachings described herein, systems and methods are provided for charge compensation. A system may include an operational transconductance amplifier including an input terminal and an output terminal, a transistor network, and a capacitive circuit. The transistor network may be coupled in a feedback loop between the input terminal and the output terminal. The capacitive circuit may be configured to compensate a charge built on a parasitic capacitance of the transistor network during operation.

Abstract: An oscillator includes a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator.

Abstract: A phase-locked loop (PLL) with a decreased frequency tuning gain KVCO and a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, KVCO, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/? of that of the second voltage to current converter, wherein ?>1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump.

Abstract: Continuous time filters and ?-? analog to digital converters and methods for process variation trim/tuning. In feed forward filters, the resistance of feed forward transconductance elements are adjusted to compensate for process variation in the GM/SC values in the filters. Since all. GM/SC values are subject to the same RC process variation, and the resistance in all feed forward transconductance elements is also subject to the same R process variation, the resistance in the feed forward transconductance elements may be adjusted in accordance with analytically predetermined factors based on a single measurement of the RC process variation for each filter to compensate for the overall RC process variation. Various embodiments are disclosed, both as feed forward filters and as ?-? analog to digital converter systems using such filters.