Patents by Inventor Tao Wei

Tao Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9906011
    Abstract: An over-current protection circuit includes a first connector, a first current measuring unit, a first switch unit, a first resistor unit, and a second connector. The first connector is electrically coupled to a power supply unit (PSU). When a current of the first resistor unit measured by the first current measuring unit is less than a first reference value, the first switch unit is turned on, and the second connector receives a first power supply from the PSU. When the current of the first resistor unit measured by the first current measuring unit is greater than or equal to the first reference value, the first switch unit is turned off, and the second connector does not receive the first power supply from the PSU.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: February 27, 2018
    Assignee: ScienBiziP Consulting(Shenzhen)Co., Ltd.
    Inventors: Ming-Tao Wei, Qi-Sheng Xu, Sung-Kuo Ku
  • Publication number: 20180016270
    Abstract: Disclosed are a series of diaza-benzofluoranthrene compounds. The present invention particularly relates to a compound represented by formula (I), pharmaceutically acceptable salts or tautomers thereof.
    Type: Application
    Filed: February 2, 2016
    Publication date: January 18, 2018
    Inventors: Shujie Yuan, Xinchun Yang, Jinlong Zhao, Daoxu Zhang, Mingda Sun, Jiaji Liu, Tao Wei, Huanan Zhao, Yunfu Luo, Chundao Yang
  • Patent number: 9853119
    Abstract: Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 26, 2017
    Assignee: Bourns, Inc.
    Inventors: Andrew J. Morrish, Tao Wei
  • Patent number: 9841301
    Abstract: The present disclosure provides a sweep velocity-locked laser pulse generator (SV-LLPG) controlled using a digital phase locked loop (DPLL) circuit. The SV-LLPG is utilized for the interrogation of sub-terahertz-range fiber structures for sensing applications that require real-time data collection with mm-level spatial resolution. A laser generates chirped laser pulses via injection current modulation and a DPLL circuit locks the optical frequency sweep velocity. A high-quality linearly chirped laser pulse with a frequency excursion of 117.69 GHz at optical communication bands using a distributed feedback laser is provided.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 12, 2017
    Assignee: RHODE ISLAND BOARD OF EDUCATION, STATE OF RHODE ISLAND AND PROVIDENCE PLANTATIONS
    Inventors: Tao Wei, Zhen Chen, Gerald Hefferman
  • Publication number: 20170344361
    Abstract: This application discloses at least a kernel repair method and apparatus. An embodiment of the method includes: loading a patch for repairing a to-be-repaired object function in a kernel, the patch being written in a memory-safe language subset of a non-memory-safe language or a memory-safe language; executing the patch using a memory-safe language engine; receiving a call request for calling a repair interface to repair the object function during the executing of the patch, wherein the repair interface is an interface provided by the memory-safe language engine and used for repairing a function; and executing the requested repair interface to repair the object function. As such, the hot patching and security of a kernel can be achieved.
    Type: Application
    Filed: September 29, 2016
    Publication date: November 30, 2017
    Inventors: Yulong ZHANG, Chenfu BAO, Tao WEI
  • Publication number: 20170221986
    Abstract: The present invention belongs to the technical field of semiconductors and discloses a copolar integrated diode, including a plurality of diode structures sharing anodes or cathodes. The copolar integrated diode comprises a semiconductor substrate; a low-doped drift region is doped on the semiconductor substrate; two or more electrodes are connected to the low-doped drift region; wherein, between the low-doped drift region and the semiconductor substrate or in the case of forming a PN junction in the low-doped drift region, the distances from the two or more electrodes to the PN junction of the diode structure are different. The present invention provides an integrated structure of a plurality of diodes, which is low in space occupancy and high in security.
    Type: Application
    Filed: July 15, 2016
    Publication date: August 3, 2017
    Inventors: Tao Wei, Richard Morgan Ho
  • Patent number: 9717939
    Abstract: The disclosure relates to a fire extinguishing composition containing a transition metal compound, comprising a salt of an organic acid of the fourth period elements in a subgroup and the group VIII; and using a pyrotechnic agent as a heat source and a power source, reacting through heat emitted by igniting the pyrotechnic agent to burn and outputting a fire extinguishing material.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: August 1, 2017
    Assignee: XI'AN WESTPEACE FIRE TECHNOLOGY CO., LTD
    Inventors: Tao Wei, Tao Ji, Shengxin Liu
  • Publication number: 20170191883
    Abstract: The present disclosure provides a novel distributed coaxial cable strain sensor that can measure a strain profile over the entire length of a cable. Individual strain sensing elements are constructed using Fabry-Perot interferometers, coaxial cable Bragg gratings, or other reflectometry-based sensing structures. By assembling three or more strain sensors together in a bundle, a coaxial cable shape sensing device can be constructed which is capable of accurate three dimensional position measurement.
    Type: Application
    Filed: December 14, 2016
    Publication date: July 6, 2017
    Applicant: Rhode Island Board of Education, State of Rhode Island and Providence Plantations
    Inventors: Tao Wei, Zhen Chen, Gerald Hefferman
  • Publication number: 20170153387
    Abstract: The present disclosure provides a novel fiber optic sensing device using ultra-weak, terahertz-range reflector structures. A fiber optic sensor device for distributed measurements (strain/temperature) includes an optical fiber detection arm having an inner core extending along a length of the optical fiber, an outer cladding surrounding the inner core, and at least one ultra-weak, terahertz-range reflector structure. Each reflector structure is comprised of two or more ultra-weak range reflectors (gratings) written at a spacing corresponding to the terahertz range and formed along a length of the inner core of the optical fiber. A narrow bandwidth, tunable laser interrogation system interrogates the optical fiber and measures changes in reflections and interference patterns caused by physical changes in the optical fiber.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 1, 2017
    Applicant: Rhode Island Board of Education, State of Rhode Island and Providence Plantations
    Inventors: Tao Wei, Zhen Chen, Gerald Hefferman
  • Publication number: 20170153130
    Abstract: The present disclosure provides a sweep velocity-locked laser pulse generator (SV-LLPG) controlled using a digital phase locked loop (DPLL) circuit. The SV-LLPG is utilized for the interrogation of sub-terahertz-range fiber structures for sensing applications that require real-time data collection with mm-level spatial resolution. A laser generates chirped laser pulses via injection current modulation and a DPLL circuit locks the optical frequency sweep velocity. A high-quality linearly chirped laser pulse with a frequency excursion of 117.69 GHz at optical communication bands using a distributed feedback laser is provided.
    Type: Application
    Filed: January 27, 2017
    Publication date: June 1, 2017
    Applicant: Rhode Island Board of Education, State of Rhode Island and Providence Plantations
    Inventors: Tao Wei, Zhen Chen, Gerald Hefferman
  • Patent number: 9662523
    Abstract: Disclosed in the present invention is a metallic oxysalt fire extinguishing composition; the fire extinguishing composition comprises a metallic oxysalt compound and a flame-retardant extinguishing component, their proportion being respectively as follows: 30%-95% of the metallic oxysalt compound and 5%-70% of the flame-retardant extinguishing component. A pyrotechnic composition is used as the heat source and the power source of the fire extinguishing composition in the present invention, by igniting the pyrotechnic composition, the fire extinguishing composition being heated and subjected to a decomposition reaction by using high temperature generated by means of combustion of the pyrotechnic composition, large quantities of substances capable of extinguishing fire being generated, and the fire extinguishing substances along with the pyrotechnic composition being ejected from the nozzle of a fire extinguishing apparatus, thus achieving the purpose of extinguishing fire.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 30, 2017
    Assignee: XI'AN WESTPEACE FIRE TECHNOLOGY CO., LTD.
    Inventors: Tao Ji, Tao Wei, Wei Tian, Shengxin Liu
  • Publication number: 20170084716
    Abstract: Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Andrew J. Morrish, Tao Wei
  • Publication number: 20160329396
    Abstract: A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventor: Tao Wei
  • Patent number: 9431532
    Abstract: A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 30, 2016
    Assignee: PowerWyse, Inc.
    Inventor: Tao Wei
  • Publication number: 20160240669
    Abstract: A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.
    Type: Application
    Filed: September 3, 2015
    Publication date: August 18, 2016
    Inventor: Tao Wei
  • Patent number: D763842
    Type: Grant
    Filed: March 1, 2015
    Date of Patent: August 16, 2016
    Assignee: OTTER PRODUCTS, LLC
    Inventors: Tao-Wei Chang, Patrick J. Nelson
  • Patent number: D765635
    Type: Grant
    Filed: March 1, 2015
    Date of Patent: September 6, 2016
    Assignee: OTTER PRODUCTS, LLC
    Inventors: Tao-Wei Chang, Ross V. Bulkley
  • Patent number: D771611
    Type: Grant
    Filed: March 1, 2015
    Date of Patent: November 15, 2016
    Assignee: Otter Products, LLC
    Inventors: Tao-Wei Chang, Ryan D. Sellden
  • Patent number: D772881
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: November 29, 2016
    Assignee: Otter Products, LLC
    Inventors: Tao-Wei Chang, Lucas B. Weller, Richard Rodriguez, John P. Fitzgerald
  • Patent number: D783835
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: April 11, 2017
    Assignee: SHENZHEN MINDRAY BIO-MEDICAL ELECTRONICS CO., LTD.
    Inventors: Peter Baird Schon, Aidan Gregory Hyde, Chun Chit Kan, Haibo Chai, Wei Qin, Tao Wei, Wei Chen, Qinglin Tao