Abstract: This application provides a fan and an electronic device. The fan includes a body, and an air duct, an air outlet and a flow guiding inlet are formed in the body; the air duct includes an air inlet area and an air outlet area, and a flow guiding member is disposed in the air outlet area; the flow guiding member and the body form a first channel, a second channel, and a third channel. After a main airflow in the air inlet area enters the first channel and the third channel, a negative pressure area is formed at the flow guiding outlet, a differential pressure exists between air pressures in the negative pressure area and the second channel, and the differential pressure enables air to enter the flow guiding cavity from the flow guiding inlet to form an induced airflow, thereby increasing an air output.

Abstract: A heterostructured antimicrobial stainless steel with improved yield strength and reduced strength-to-ductility trade-off and methods for synthesizing the same are provided. The heterostructured antimicrobial stainless steel has a plurality of mechanically strengthening mechanisms including: interstitial solid solution alloying elements; substitutional solid solution alloying elements; twins; multiphasic interfaces formed with face-centered cubic austenite phase and body-centered cubic martensite phase; statistically stored dislocations; strain-induced phase transformation; geometrically necessary dislocations pile-ups; stacking faults; precipitates; high density of grain boundaries; and HDI strengthening.

Abstract: Techniques are disclosed for analyzing and learning behavior in an acquired stream of video frames. In one embodiment, a trajectory analyzer clusters trajectories of objects depicted in video frames and builds a trajectory model including the trajectory clusters, a prior probability of assigning a trajectory to each cluster, and an intra-cluster probability distribution indicating the probability that a trajectory mapping to each cluster is least various distances away from the cluster. Given a new trajectory, a score indicating how unusual the trajectory is may be computed based on the product of the probability of the trajectory mapping to a particular cluster and the intra-cluster probability of the trajectory being a computed distance from the cluster. The distance used to match the trajectory to the cluster and determine intra-cluster probability is computed using a parallel Needleman-Wunsch algorithm, with cells in antidiagonals of a matrix and connected sub-matrices being computed in parallel.

Abstract: Embodiments of this application provide a fan apparatus and an electronic device. The fan apparatus includes a first housing, a second housing, a fan blade unit, and a fence member located in the first housing. The fan blade unit is rotatably disposed in an accommodating cavity in the first housing. The fence member is located on a circumferential outer side of the fan blade unit. The second housing is covered on the first housing and the fence member, and encloses at least one resonant cavity together with the first housing and the fence member. The resonant cavity communicates with the accommodating cavity through a muffling hole on a cavity wall. Air in the resonant cavity resonates under excitation by an airflow of the fan blade unit. The fan apparatus of this application helps alleviate a noise problem caused by a fan with a high rotational speed, without affecting a heat dissipation effect of an existing electronic device.

Abstract: A method of creating a ductile, work-hardened, nanotwinned, austenite/martensite nano-lamellar nanostructure in an austenite steel alloy. Briefly, raw materials with high-purity are smelted to obtain an as-cast steel alloy ingot, which will be subjected to homogenization and cold-roll treatment for reduction. The homogenized and cold-rolled steel alloy ingot is further recrystallized to eliminate any possible casting defects and form an as-recrystallized steel alloy having a single face-centered cubic structure with recrystallized grains. The as-recrystallized steel alloy is cold-rolled again for forming a nanotwinned austenite structure and for forming martensite lamellae along nanotwin boundaries such that an austenite/martensite nano-lamellar structure in the steel alloy.

Abstract: A data processing method includes: in response to a service enabling operation in a video application, enabling a video recording service in the video application; collecting, using the video recording service, user voice data; determining and identifying a target text that matches prompting text data associated with the video recording service; and acquiring target video data corresponding to the video recording service until a text position of the target text in the prompting text data is at an end of the prompting text data. Embodiments of this application improve the effectiveness of teleprompting functions during a video recording, and the quality of a recorded video may further be improved.

Abstract: There is included a method and apparatus comprising computer code configured to cause a processor or processors to perform obtaining video data including at least one body part of a person, selecting keypoints of the at least one body part based on a predetermined rehabilitation category, extracting a motion feature of the at least one body part from the video data, scoring the motion feature based on the predetermined rehabilitation category, and generating a display illustrating the motion feature and said scoring of the motion feature.

Abstract: Techniques are disclosed for generating a syntax for a neuro-linguistic model of input data obtained from one or more sources. A stream of words of a dictionary built from a sequence of symbols are received. The symbols are generated from an ordered stream of normalized vectors generated from input data. Statistics for combinations of words co-occurring in the stream are evaluated. The statistics includes a frequency upon which the combinations of words co-occur. A model of combinations of words based on the evaluated statistics is updated. The model identifies statistically relevant words. A connected graph is generated. Each node in the connected graph represents one of the words in the stream. Edges connecting the nodes represent a probabilistic relationship between words in the stream. Phrases are identified based on the connected graph.

Abstract: Provided in embodiments of the present application are a head mechanism and a fan apparatus. The head mechanism includes: a casing, where a primary air inlet and an air outlet are provided on a circumferential side wall of the casing, and an auxiliary air inlet is provided on an axial wall surface of the casing; and a centrifugal volute arranged in the casing, where a centrifugal fan is arranged in the centrifugal volute, and an air duct outlet corresponding to the air outlet and an air duct inlet corresponding to the auxiliary air inlet are provided on the centrifugal volute; and air flowing from the primary air inlet and the auxiliary air inlet flows into the centrifugal volute through the air duct inlet. According to the embodiment of the present application, since the primary air inlet located on the circumferential side wall is provided.

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another.

Abstract: A method and an apparatus of identifying at least one target object for a security inspection CT are provided. The method includes: performing a dimension reduction on three-dimensional CT data to generate a plurality of two-dimensional dimension-reduced views (S10); performing a target identification on a plurality of two-dimensional views to obtain a set of two-dimensional semantic descriptions of the at least one target object, where the plurality of two-dimensional views include the plurality of two-dimensional dimension-reduced views (S20); and performing a dimension increase on the set of two-dimensional semantic descriptions to obtain a three-dimensional recognition result of the at least one target object (S30).

Abstract: The present disclosure provides a drive circuit of a display panel, a method for driving the same, and a display device, and relates to the field of display technologies. The drive circuit includes: a power supply circuit, an adapter circuit board, and a voltage regulation circuit. The adapter circuit board transmits a power supply voltage supplied by the power supply circuit to light-emitting elements in the display panel. The voltage regulation circuit regulates, based on an ideal operating voltage of the light-emitting element under a certain grayscale and a wiring voltage drop on a wiring coupled to the light-emitting element, the power supply voltage supplied by the power supply circuit. That is, the voltage regulation circuit flexibly regulates, based on a grayscale of a screen displayed by the display panel, the power supply voltage supplied by the power supply circuit to the light-emitting element.

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a pad-out structure disposed on the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal in contact with the first side of the first semiconductor layer and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; and a plate line extending in the second direction.

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a peripheral circuit bonded to the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; plate lines extending in the second direction; and a first dielectric layer disposed between the semiconductor body and the word line and the plate line.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure is sandwiched between the first semiconductor structure and the fourth semiconductor structure, and the fourth semiconductor is sandwiched between the second semiconductor structure and the third semiconductor structure.

Abstract: A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

Abstract: A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.