Patents by Inventor Taotao Zhu
Taotao Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230391775Abstract: A compound represented by formula (I), and a racemate, a stereoisomer, a tautomer, an isotopic label, an N-oxide, a hydrate, a solvate, a polymorph, a metabolite, a pharmaceutically acceptable salt, a pharmaceutically acceptable ester, or a prodrug compound thereof are provided. This class of compounds has a good LRRK2 kinase regulation and inhibition and can be used for the treatment of an LRRK2 kinase activity-associated conditions and diseases, such as proliferative diseases, protein kinase-associated diseases, lysosomal diseases, Tau diseases, and diseases caused by decreased dopamine levels. etc.Type: ApplicationFiled: October 27, 2021Publication date: December 7, 2023Inventors: Yan XIA, Zengshan GUO, Ziqing JIANG, Xizhi WANG, Taotao ZHU, Chuan WANG, Lang ZHUO
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Publication number: 20230380651Abstract: A cleaning implement for cleaning a target surface is provided that includes an erodible foam adapted to contact a surface to be cleaned and a rheological solid composition comprising a crystallizing agent and an aqueous phase.Type: ApplicationFiled: August 15, 2023Publication date: November 30, 2023Inventors: Matthew Lawrence LYNCH, Brandon Philip ILLIE, Taotao ZHU, Jamie Lynn DRIA, Randall Glenn MARSH
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Patent number: 11812909Abstract: A cleaning implement for cleaning a target surface is provided that includes an erodible foam adapted to contact a surface to be cleaned and a rheological solid composition comprising a crystallizing agent and an aqueous phase.Type: GrantFiled: April 8, 2021Date of Patent: November 14, 2023Assignee: The Procter & Gamble CompanyInventors: Matthew Lawrence Lynch, Brandon Philip Illie, Taotao Zhu, Jamie Lynn Dria, Randall Glenn Marsh
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Publication number: 20230050077Abstract: The present disclosure relates to compositions comprising an aqueous solution of at least about 70% by weight water in combination with selected fatty acid salts and optionally an alcohol and/or a cooling sensate, as well as methods of using the same to treat symptoms of hot flashes. The fatty acid salts form fiber-like crystalline particles that together form a self-supporting mesh structure with voids, the aqueous solution being contained in the voids. When the composition is compressed above a critical stress, the mesh allows for the entrapped aqueous solution to be expressed.Type: ApplicationFiled: October 10, 2022Publication date: February 16, 2023Inventors: Connie Michelle DUNAWAY, Samantha Chen-Yee WANG, Mary Jane WATSON, Matthew Lawrence LYNCH, Jamie Lynn DRIA, Brandon Philip ILLIE, Taotao ZHU, Dorothy Angela HALL, Beth Ann SCHUBERT
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Patent number: 11550572Abstract: This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index.Type: GrantFiled: October 25, 2021Date of Patent: January 10, 2023Assignee: T-Head (Shanghai) Semiconductor Co., Ltd.Inventors: Jiahui Luo, Taotao Zhu, Chang Liu
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Patent number: 11550646Abstract: The present disclosure provides a method and a system of verifying access by a multi-core interconnect to an L2 cache in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry detects, in real time, interactions among a multi-core interconnects system, all single-core processors, an L2 cache and a primary memory, and sends collected transmission information to an L2 cache expectation generator and a check circuitry. The L2 cache expectation generator obtains information from a global memory precise control circuitry according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnect's access accuracy to the L2 cache without delay.Type: GrantFiled: May 31, 2019Date of Patent: January 10, 2023Assignee: C-SKY Microsystems Co., Ltd.Inventor: Taotao Zhu
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Patent number: 11436146Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.Type: GrantFiled: July 24, 2020Date of Patent: September 6, 2022Assignee: Alibaba Group Holding LimitedInventors: Yimin Lu, Xiaoyan Xiang, Taotao Zhu, Chaojun Zhao
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Patent number: 11409636Abstract: The present disclosure discloses a debug unit, comprising: a write register configured to store kernel write data written by a kernel of a processor, wherein the processor is communicatively coupled to a debugger configured to read the kernel write data, wherein the kernel write data is associated with a kernel write flag bit to indicate data validity of the kernel write data; and a control unit including circuitry configured to control access to the write register by the kernel of the processor and the debugger based on data validity indicated by the kernel write flag bit. The present disclosure further discloses a corresponding processor including the debug unit, a corresponding debugger communicatively coupled to the processor, and a corresponding debug system including the processor coupled to the debugger.Type: GrantFiled: March 18, 2020Date of Patent: August 9, 2022Assignee: Alibaba Group Holding LimitedInventors: Taotao Zhu, Chen Chen
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Patent number: 11409531Abstract: Disclosed is a processor having multiple operating modes, comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; and an access control interface communicatively coupled to the resource mapping circuitry and the second mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry.Type: GrantFiled: March 24, 2020Date of Patent: August 9, 2022Assignee: C-SKY Microsystems Co., Ltd.Inventors: Chen Chen, Taotao Zhu, Chang Liu
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Patent number: 11354256Abstract: The present invention discloses a multi-core interconnection bus, including a request transceiver module adapted to receive a data request from a processor core, and forward the data request to a snoop and caching module through a request execution module, where the data request includes a request address; the snoop and caching module adapted to look up cache data validity information of the request address, acquire data from a shared cache, and sequentially return the cache data validity information and the data acquired from the shared cache to the request execution module; and the request execution module adapted to determine, based on the cache data validity information, a target processor core whose local cache stores valid data, forward the data request to the target processor core, and receive returned data; and determine response data from the data returned by the target processor core and that returned by the snoop and caching module, and return, through the request transceiver module, the response dType: GrantFiled: September 15, 2020Date of Patent: June 7, 2022Assignee: Alibaba Group Holding LimitedInventors: Xiaoyan Xiang, Taotao Zhu
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Publication number: 20220147351Abstract: This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index.Type: ApplicationFiled: October 25, 2021Publication date: May 12, 2022Inventors: Jiahui LUO, Taotao ZHU, Chang LIU
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Patent number: 11275707Abstract: The present invention discloses a multi-core processor and an inter-core data forwarding method. The multi-core processor includes a plurality of processor cores and a multi-core interconnection bus.Type: GrantFiled: September 4, 2020Date of Patent: March 15, 2022Assignee: Alibaba Group Holding LimitedInventors: Xiaoyan Xiang, Taotao Zhu, Feng Zhu
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Publication number: 20220010245Abstract: A cleaning article for cleaning a target surface is provided that includes a substrate having a first surface and second surface and a rheological solid composition comprising a crystallizing agent and an aqueous phase.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Inventors: Matthew Lawrence LYNCH, Scott Kendyl STANLEY, Brandon Philip ILLIE, Taotao ZHU, Jamie Lynn DRIA
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Patent number: 11215665Abstract: The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers.Type: GrantFiled: April 26, 2019Date of Patent: January 4, 2022Assignee: C-SKY Microsystems Co., Ltd.Inventors: Taotao Zhu, Yubo Guo
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Patent number: 11182318Abstract: Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priorityType: GrantFiled: March 24, 2020Date of Patent: November 23, 2021Assignee: Alibaba Group Holding LimitedInventors: Chaojun Zhao, Xiaoyan Xiang, Chen Chen, Taotao Zhu
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Publication number: 20210357327Abstract: The present disclosure provides a method and a system of verifying access by a multi-core interconnect to an L2 cache in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry detects, in real time, interactions among a multi-core interconnects system, all single-core processors, an L2 cache and a primary memory, and sends collected transmission information to an L2 cache expectation generator and a check circuitry. The L2 cache expectation generator obtains information from a global memory precise control circuitry according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnect's access accuracy to the L2 cache without delay.Type: ApplicationFiled: May 31, 2019Publication date: November 18, 2021Inventor: Taotao ZHU
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Publication number: 20210341566Abstract: The present disclosure discloses a method for positioning a device. The method includes obtaining a location parameter associated with the device. The location parameter includes at least one of first location information or speed information. The method also includes obtaining an orientation parameter associated with the device. The orientation parameter includes at least one of first orientation information or angle velocity information. Further, the method includes determining target location information of the device by performing a first fusion calculation based on the location parameter and determining target orientation information of the device by performing a second fusion calculation based on the orientation parameter.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Applicant: SHENZHEN HANYANG TECHNOLOGY CO., LTD.Inventors: Yang HUANG, Taotao ZHU, Anyang TIAN, Qingqing QIAO
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Publication number: 20210330565Abstract: A rheological solid composition comprising a crystallizing agent and an aqueous phase.Type: ApplicationFiled: April 8, 2021Publication date: October 28, 2021Inventors: Matthew Lawrence Lynch, Brandon Philip Illie, Taotao Zhu, Philip Andrew Sawin, Jamie Lynn Dria
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Publication number: 20210322322Abstract: A rheological solid oral composition comprising a crystallizing agent, an aqueous phase, and an oral active agent.Type: ApplicationFiled: April 8, 2021Publication date: October 21, 2021Inventors: Matthew Lawrence Lynch, Scott Kendyl Stanley, Brandon Philip Illie, Taotao Zhu, Jamie Lynn Dria, Ashraf Traboulsi
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Patent number: D998649Type: GrantFiled: February 9, 2022Date of Patent: September 12, 2023Assignee: SHENZHEN HANYANG TECHNOLOGY CO., LTDInventors: Yang Huang, Taotao Zhu