Abstract: A rheological solid shave composition. The rheological solid shave composition has a crystallizing agent, an active and an aqueous phase.

Abstract: An oral care product including an oral care rheological solid composition including a crystallizing agent, an aqueous phase, and oral care adjunct ingredient. The oral care product can be a floss, a dentifrice, and/or a whitening product. A method for making an oral care rheological solid composition by providing water, providing crystallizing agent, providing NaCl in an amount of about 10% or less, by weight of the oral care rheological solid composition; and mixing the water, crystallizing agent, and NaCl to produce the oral care rheological solid composition.

Abstract: A cleaning article for cleaning a target surface is provided that includes a substrate having a first surface and second surface and a rheological solid composition comprising a crystallizing agent and an aqueous phase.

Abstract: A rheological solid personal care composition comprises a crystallizing agent, a suspension agent, an insoluble active, and an aqueous phase.

Abstract: Rheological solid self-supporting liquid expressing composition comprising more than 80% water having a crystallizing agent, suspension agent, and insoluble active.

Abstract: A cleaning implement for cleaning a target surface is provided that includes an erodible foam adapted to contact a surface to be cleaned and a rheological solid composition comprising a crystallizing agent and an aqueous phase.

Abstract: A rheological solid composition comprising a crystallizing agent and an aqueous phase.

Abstract: The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers.

Abstract: The present invention discloses a multi-core interconnection bus, including a request transceiver module adapted to receive a data request from a processor core, and forward the data request to a snoop and caching module through a request execution module, where the data request includes a request address; the snoop and caching module adapted to look up cache data validity information of the request address, acquire data from a shared cache, and sequentially return the cache data validity information and the data acquired from the shared cache to the request execution module; and the request execution module adapted to determine, based on the cache data validity information, a target processor core whose local cache stores valid data, forward the data request to the target processor core, and receive returned data; and determine response data from the data returned by the target processor core and that returned by the snoop and caching module, and return, through the request transceiver module, the response d

Abstract: A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.

Abstract: A processor core, a processor, an apparatus, and a method are disclosed. The processor core is coupled to a translation lookaside buffer and a first memory. The processor core further includes a memory processing module that includes: an instruction processing unit, adapted to identify a virtual memory operation instruction and send the virtual memory operation instruction to a bus request transceiver module; the bus request transceiver module, adapted to send the virtual memory operation instruction to an external interconnection unit; a forwarding request transceiver unit, adapted to receive the virtual memory operation instruction broadcast by the interconnection unit and send the virtual memory operation instruction to the virtual memory operation unit; and the virtual memory operation unit, adapted to perform a virtual memory operation according to the virtual memory operation instruction. An initiation core sends the virtual memory operation instruction to the interconnection unit.

Abstract: The present invention discloses a multi-core processor and an inter-core data forwarding method. The multi-core processor includes a plurality of processor cores and a multi-core interconnection bus.

Abstract: Disclosed is a processor having multiple operating modes, comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; and an access control interface communicatively coupled to the resource mapping circuitry and the second mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry.

Abstract: Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority

Abstract: The present disclosure discloses a debug unit, comprising: a write register configured to store kernel write data written by a kernel of a processor, wherein the processor is communicatively coupled to a debugger configured to read the kernel write data, wherein the kernel write data is associated with a kernel write flag bit to indicate data validity of the kernel write data; and a control unit including circuitry configured to control access to the write register by the kernel of the processor and the debugger based on data validity indicated by the kernel write flag bit. The present disclosure further discloses a corresponding processor including the debug unit, a corresponding debugger communicatively coupled to the processor, and a corresponding debug system including the processor coupled to the debugger.

Abstract: The present invention generally relates to microparticles and, in particular, to systems and methods for encapsulation within microparticles. In one aspect, the present invention is generally directed to microparticles containing entities therein, where the entities contain an agent that can be released from the microparticles, e.g., via diffusion. In some cases, the agent may be released from the microparticles without disruption of the microparticles. The entities may be, for instance, polymeric particles, hydrogel particles, droplets of fluid, etc. The entities may be contained within a fluid that is, in turn, encapsulated within the microparticle. The agent may be released from the entity into the fluid, and then from the fluid through the microparticle. In such fashion, the release of agent from the microparticle may be controlled, e.g., over relatively long time scales.

Abstract: The present invention generally relates to microparticles and, in particular, to systems and methods for encapsulation within microparticles. In one aspect, the present invention is generally directed to microparticles containing entities therein, where the entities contain an agent that can be released from the microparticles, e.g., via diffusion. In some cases, the agent may be released from the microparticles without disruption of the microparticles. The entities may be, for instance, polymeric particles, hydrogel particles, droplets of fluid, etc. The entities may be contained within a fluid that is, in turn, encapsulated within the microparticle. The agent may be released from the entity into the fluid, and then from the fluid through the microparticle. In such fashion, the release of agent from the microparticle may be controlled, e.g., over relatively long time scales.

Abstract: Embodiments of the present disclosure provide for devices, methods for separating particles, and the like.

Abstract: Embodiments of the present disclosure provide for devices, methods for separating particles, and the like.

Abstract: The present invention generally relates to microparticles and, in particular, to systems and methods for encapsulation within microparticles. In one aspect, the present invention is generally directed to microparticles containing entities therein, where the entities contain an agent that can be released from the microparticles, e.g., via diffusion. In some cases, the agent may be released from the microparticles without disruption of the microparticles. The entities may be, for instance, polymeric particles, hydrogel particles, droplets of fluid, etc. The entities may be contained within a fluid that is, in turn, encapsulated within the microparticle. The agent may be released from the entity into the fluid, and then from the fluid through the microparticle. In such fashion, the release of agent from the microparticle may be controlled, e.g., over relatively long time scales.