Patents by Inventor Tarek A. Ibrahim

Tarek A. Ibrahim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12381029
    Abstract: Embodiments disclosed herein include electronic packages with embedded inductors and methods of forming such electronic packages. In an embodiment, the electronic package comprises a package core, and a plated through hole (PTH) through a thickness of the package core. In an embodiment, the electronic package further and a magnetic shell around a perimeter of the PTH, where a height of the magnetic shell is less than the thickness of the package core. In an embodiment, the magnetic shell comprises a substantially vertical sidewall and a bottom surface that is tapered.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 5, 2025
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Krishna Bharath, Haifa Hariri, Tarek A. Ibrahim
  • Publication number: 20250226323
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
    Type: Application
    Filed: March 25, 2025
    Publication date: July 10, 2025
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
  • Patent number: 12345931
    Abstract: In an optical circuit, a substrate can define a cavity that extends into a substrate front surface. A sidewall of the cavity can include a substrate optical port. An optical path can extend through the substrate from a connector optical port to the substrate optical port. A photonic integrated circuit (PIC) can attach to the substrate. A PIC front surface can include a plurality of electrical connections. A PIC edge surface can extend around at least a portion of a perimeter of the PIC between the PIC front surface and a PIC back surface. A PIC optical port can be disposed on the PIC edge surface and can accept or emit an optical beam along a PIC optical axis. The PIC optical axis can be aligned with the substrate optical port when the PIC is attached to the substrate.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Eric J. M. Moret, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim
  • Patent number: 12345932
    Abstract: Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Bai Nie, Pooya Tadayon, Leonel R. Arana, Yonggang Li, Changhua Liu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Hari Mahalingam, Benjamin Duong
  • Patent number: 12334453
    Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: June 17, 2025
    Assignee: Intel Corporation
    Inventors: Nicholas Neal, Nicholas S. Haehn, Sergio Chan Arguedas, Edvin Cetegen, Jacob Vehonsky, Steve S. Cho, Rahul Jain, Antariksh Rao Pratap Singh, Tarek A. Ibrahim, Thomas Heaton
  • Patent number: 12327797
    Abstract: Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: June 10, 2025
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Tarek A. Ibrahim, Gang Duan, Sai Vadlamani, Bharat Prasad Penmecha
  • Publication number: 20250183180
    Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 5, 2025
    Inventors: Brandon C. MARIN, Robert Alan MAY, Minglu LIU, Bohan SHAN, Jason M. GAMBA, Lilia MAY, Tarek A. IBRAHIM, Hiroki TANAKA, Srinivas Venkata Ramanuja PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Suddhasattwa NAD, Benjamin DUONG, Haobo CHEN, Xiao LIU, Xiyu HU, Wei WEI, Bai NIE, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Yiqun BAI
  • Publication number: 20250112179
    Abstract: Techniques for a coaxial inductor in a glass core are disclosed. In an illustrative embodiment, an inductor is positioned in a cavity of a glass core. The inductor includes a conductive via extending through the glass core surrounded by a magnetic material. A buffer layer is positioned between the edges of the cavity of the glass core and the inductor. The buffer can prevent or mitigate any stress caused by changes in temperature and different coefficients of thermal expansion of the glass core and the inductor. The inductor may form part of a fully integrated voltage regulator (FIVR), which provides a stable voltage source to a semiconductor die such as a processor.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Brandon Christian Marin, Tarek A. Ibrahim, Mohammad Mamunur Rahman, Srinivas V. Pietambaram, Sashi Shekhar Kandanur
  • Publication number: 20250107112
    Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Inventors: Brandon C. MARIN, Srinivas PIETAMBARAM, Mohammad Mamunur RAHMAN, Sashi Shekhar KANDANUR, Aleksandar ALEKSOV, Tarek A. IBRAHIM, Rahul N. MANEPALLI
  • Publication number: 20250096143
    Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon C. Marin, Tarek A. Ibrahim, Srinivas V. Pietambaram, Gang Duan
  • Publication number: 20250096053
    Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon C. Marin, Bohan Shan, Tarek A. Ibrahim, Srinivas V. Pietambaram, Gang Duan, Benjamin T. Duong, Suddhasattwa Nad
  • Patent number: 12249584
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: March 11, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Benjamin T. Duong, Srinivas V. Pietambaram, Tarek A. Ibrahim
  • Publication number: 20250070030
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
    Type: Application
    Filed: November 11, 2024
    Publication date: February 27, 2025
    Inventors: Sanka GANESAN, Ram VISWANATH, Xavier Francois BRUN, Tarek A. IBRAHIM, Jason M. GAMBA, Manish DUBEY, Robert Alan MAY
  • Publication number: 20250060531
    Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICS. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Intel Corporation
    Inventors: Omkar G. Karhade, Xiaoqian Li, Tarek A. Ibrahim, Ravindranath Vithal Mahajan, Nitin A. Deshpande
  • Patent number: 12230564
    Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Brandon Christian Marin, Tarek A. Ibrahim, Karumbu Nathan Meyyappan, Valery Ouvarov-Bancalero, Dingying Xu
  • Publication number: 20250004225
    Abstract: Technologies for substrate features for a pluggable optical connectors in an integrated circuit package are disclosed. In the illustrative embodiment, a substrate includes a cavity cut through a substrate of the integrated circuit package. Sidewalls of the cavity establish coarse lateral alignment features for an optical plug. The optical plug and optical socket include additional alignment features to more precisely align optical fibers in the optical plug to an optical interposer mounted on the substrate. The cavity cut through the substrate may also include indents that can mate with protrusions of the optical plug to retain the optical plug. The optical interposer may be mounted on a recessed shelf in the substrate.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Mohanraj Prabhugoud, David Shia, Tarek A. Ibrahim, Yuxin Fang
  • Patent number: 12181710
    Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Xiaoqian Li, Tarek A. Ibrahim, Ravindranath Vithal Mahajan, Nitin A. Deshpande
  • Patent number: 12176292
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
    Type: Grant
    Filed: October 2, 2023
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
  • Patent number: 12068172
    Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Tarek A. Ibrahim, Rahul N. Manepalli, Wei-Lun K. Jen, Steve S. Cho, Jason M. Gamba, Javier Soto Gonzalez
  • Publication number: 20240217216
    Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Kristof DARMAWIKARTA, Tarek A. IBRAHIM, Srinivas V. PIETAMBARAM, Dilan SENEVIRATNE, Jieying KONG, Thomas HEATON, Whitney BRYKS, Vinith BEJUGAM, Junxin WANG, Gang DUAN