Patents by Inventor Taro Hirai

Taro Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030058629
    Abstract: A wiring substrate for used in a small electronic component. The wiring substrate comprises: an insulating substrate; and a conductive land portion which is formed on a first surface of the insulating substrate and on which an electronic element is to be mounted via conductive adhesive to electrically couple an electrode of the electronic element with the conductive land portion. The thickness of the peripheral portion of the conductive land portion which surrounds the electronic element is thicker than that of the central portion of the conductive land portion. The insulating substrate may also have a conductive land portion which is formed on a second surface of the insulating substrate and which is electrically coupled with the conductive land portion formed on the first surface of the insulating substrate via a through hole penetrating through the insulating substrate.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 27, 2003
    Inventors: Taro Hirai, Gorou Ikegami
  • Publication number: 20030036220
    Abstract: In a method for manufacturing a printed circuit board, openings are perforated in a first resin substrate. Then, a conductive layer is formed on a surface of the first resin substrate and within the openings of the first resin substrate. Then, a second resin substrate is adhered to the conductive layer by an adhesive layer. Then, the first resin substrate is peeled off from the conductive layer, so that the conductive layer is transferred from the first resin substrate to the second resin substrate.
    Type: Application
    Filed: July 25, 2002
    Publication date: February 20, 2003
    Inventors: Gorou Ikegami, Taro Hirai
  • Publication number: 20030006489
    Abstract: A flexible wiring substrate for coupling between a semiconductor element and a circuit substrate. The flexible wiring substrate comprises a base material layer made of insulating and flexible material, and wiring conductors formed on the base material layer. The wiring conductors are formed of at least one electroless plated layer and at least one electroplated layer formed on the at least one electroless plated layer. The wiring conductors are formed apart from a peripheral edge portion of the base material layer. A power supply line for electroplating used for forming the electroplated layer does not remain on the base material layer. The wiring conductors have, for example, a multi-layer structure comprising an electroless plated copper layer formed on the base material layer, an electroplated copper layer formed on the electroless plated copper layer, an electroplated nickel layer formed on the electroplated copper layer, and an electroplated gold layer formed on the electroplated nickel layer.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 9, 2003
    Inventors: Kenzo Fujii, Taro Hirai
  • Patent number: 6492597
    Abstract: A wiring substrate includes an insulating layer (1) formed with a tapered through-hole (2), a first wiring layer (3) covering an upper surface of the insulating layer (1) therewith, a second wiring layer (4) covering a lower surface of the insulating layer therewith (1), and an electrically conductive layer (5) covering an inner surface (2a) of the through-hole (2) and closing the tapered through-hole (2) at a bottom of the tapered through-hole (2).
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: December 10, 2002
    Assignee: NEC Corporation
    Inventors: Kenzo Fujii, Taro Hirai
  • Publication number: 20010002625
    Abstract: A wiring substrate includes an insulating layer (1) formed with a tapered through-hole (2), a first wiring layer (3) covering an upper surface of the insulating layer (1) therewith, a second wiring layer (4) covering a lower surface of the insulating layer therewith (1), and an electrically conductive layer (5) covering an inner surface (2a) of the through-hole (2) and closing the tapered through-hole (2) at a bottom of the tapered through-hole (2).
    Type: Application
    Filed: December 20, 2000
    Publication date: June 7, 2001
    Applicant: NEC CORPORATION
    Inventors: Kenzo Fujii, Taro Hirai
  • Patent number: 5881355
    Abstract: A method of fabricating a cathode member or pellet is provided, which realizes the sufficiently large increase of the electron emission capability by the current activation process and that prevents the maximum cathode current from being lowered as long as an electron emissive agent exists in the cathode member. First, (a) a nickel powder and a rare-earth-metal oxide powder are provided. (b) The nickel powder and the rare-earth-metal oxide powder are uniformly mixed together, thereby producing a first powder mixture. (c) The first powder mixture is heated in a hydrogen atmosphere, an inert atmosphere, or a vacuum atmosphere, thereby producing an intermetallic compound of nickel and the rare-earth metal in the first powder mixture. (d) The first powder mixture containing the intermetallic compound is uniformly mixed with an electron-emissive agent powder, thereby producing a second powder mixture. (e) The second powder mixture is sintered by a HIP process, thereby forming a cathode member.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventors: Toshikazu Sugimura, Maki Narita, Taro Hirai, Shoichi Hata