Patents by Inventor Taro Sugizaki

Taro Sugizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080042165
    Abstract: A semiconductor device includes a thyristor configured to be formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, and have a gate formed over the third region. The first to fourth regions are formed in a silicon germanium region or germanium region.
    Type: Application
    Filed: July 26, 2007
    Publication date: February 21, 2008
    Applicant: Sony Corporation
    Inventor: Taro Sugizaki
  • Publication number: 20080002463
    Abstract: A semiconductor device includes a bulk semiconductor substrate, a plurality of storage elements, a bit line, a first voltage being applied to the first region side of the thyristor, and a voltage lower than the first voltage being applied to a word line. The plurality of storage elements formed on the bulk semiconductor substrate and each including a thyristor formed on the bulk semiconductor substrate and including a first region of a first conductor type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type and a fourth region of the second conduction type jointed together in order, a gate electrode formed on the third region, and a field effect transistor formed on the semiconductor substrate on which the thyristor is formed and connected to the fourth region of the thyristor.
    Type: Application
    Filed: June 13, 2007
    Publication date: January 3, 2008
    Inventor: Taro Sugizaki
  • Publication number: 20070295987
    Abstract: A semiconductor device includes: a bulk semiconductor substrate; a thyristor formed in the bulk semiconductor substrate; a gate electrode formed at the third region; and a well region. The thyristor included a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, junctioned in order. The well region of the second conduction type is formed in the bulk semiconductor substrate, the third region is formed in the well region. A first voltage is impressed on the first region side of the thyristor, a second voltage higher than the first voltage is impressed on the fourth region side of the thyristor, and a voltage higher than or equal to the first voltage is impressed on the well region.
    Type: Application
    Filed: May 21, 2007
    Publication date: December 27, 2007
    Applicant: Sony Corporation
    Inventor: Taro Sugizaki
  • Publication number: 20070228454
    Abstract: The semiconductor memory device according to the present invention includes a charge storage layer 26 formed over a semiconductor substrate 10 and including a plurality of particles 16 as charge storage bodies in insulating films 12, 24, and a gate electrode 30 formed over the charge storage layer 26, in which the particles 16 are formed of metal oxide or metal nitride.
    Type: Application
    Filed: May 25, 2007
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Taro Sugizaki
  • Publication number: 20070138501
    Abstract: A semiconductor device has a thyristor including a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, in sequential junction, and has a gate electrode at the third region, wherein the second region is formed in a semiconductor substrate, and the first region is formed over the second region. A part of the region of a thyristor is thus provided with a laminate structure, whereby a reduction in element area can be achieved, and an enhanced punch-through resistance can be attained.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 21, 2007
    Applicant: Sony Corporation
    Inventors: Taro Sugizaki, Motoaki Nakamura, Motonari Honda
  • Publication number: 20070012945
    Abstract: The present invention is to provide a semiconductor device including: a semiconductor layer that has a first-conductivity-type region, a second-conductivity-type region, a first-conductivity-type region, and a second-conductivity-type region that are adjacent to each other in that order; first and second electrodes that are connected to the first-conductivity-type region and the second-conductivity-type region, respectively, at both ends of the semiconductor layer; and a gate electrode that is coupled to the second-conductivity-type region or the first-conductivity-type region in an intermediate area of the semiconductor layer, the gate electrode being provided over a plurality of faces of a semiconductor layer portion serving as the second-conductivity-type region or the first-conductivity-type region in the intermediate area.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 18, 2007
    Applicant: Sony Corporation
    Inventor: Taro Sugizaki
  • Patent number: 6984267
    Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: January 10, 2006
    Assignee: Fujitsu Limited
    Inventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
  • Publication number: 20030222303
    Abstract: A non-volatile semiconductor memory device comprise a source region 44 and a drain region 46 formed in a semiconductor substrate 30; a gate electrode 36 formed on the semiconductor substrate between the source region and the drain region with a first insulation film 32 formed between the gate electrode and the semiconductor substrate; and a charge accumulation region 42a, 42b of a dielectric material, which is formed on at least either of the side wall of the gate electrode on the side of the source region and the side wall of the gate electrode on the side of the drain region. Accordingly, charges accumulated on the side of the source region 44 and the charges accumulated on the side of the drain region 46 can be easily spatially isolated from each other.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 4, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masatoshi Fukuda, Taro Sugizaki, Toshiro Nakanishi, Yasuo Nara
  • Patent number: 6541393
    Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: April 1, 2003
    Assignee: Fujitsu Limited
    Inventors: Taro Sugizaki, Toshiro Nakanishi, Kyoichi Suguro, Atsushi Murakoshi
  • Publication number: 20030022523
    Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.
    Type: Application
    Filed: September 6, 2002
    Publication date: January 30, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
  • Patent number: 6468926
    Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: October 22, 2002
    Assignee: Fujitsu Limited
    Inventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
  • Publication number: 20010018274
    Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 30, 2001
    Applicant: Fujitsu Limited and Kabushiki Kaisha Toshiba
    Inventors: Taro Sugizaki, Toshiro Nakanishi, Kyoichi Suguro, Atsushi Murakoshi