Patents by Inventor Tatsuaki Tsukuda

Tatsuaki Tsukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153854
    Abstract: A semiconductor device includes a wiring substrate including a plurality of wiring layers, and a semiconductor chip including a first analog circuit. A power supply potential pattern capable of supplying a first power supply potential to the first analog circuit and a reference potential pattern capable of supplying a first reference potential to the first analog circuit are electrically connected with the first analog circuit. The power supply potential pattern is provided in a first wiring layer which is the nearest to a lower surface of the wiring substrate among the plurality of wiring layers. The reference potential pattern is provided in a second wiring layer which is the next nearest to the lower surface after the first wiring layer. The power supply potential pattern and the reference potential pattern extend in the same direction as each other while mutually overlapping with each other in transparent plan view.
    Type: Application
    Filed: July 25, 2023
    Publication date: May 9, 2024
    Inventors: Keita TSUCHIYA, Tatsuaki TSUKUDA
  • Publication number: 20240006275
    Abstract: A source pad electrically coupled with a source of a MOSFET of a semiconductor chip and located at a position below a lead in cross-sectional view is electrically connected with the lead for source via a conductive member bonded to the source pad and a wire bonded to the conductive member.
    Type: Application
    Filed: April 26, 2023
    Publication date: January 4, 2024
    Inventors: Noriko NUMATA, Koichi HASEGAWA, Tatsuaki TSUKUDA
  • Publication number: 20230144840
    Abstract: A semiconductor device includes a semiconductor chip hazing a non-overlapping region in which a source pad for main transistor and a clip do not overlap with each other. At this time, a sense transistor is arranged in a region of the non-overlapping region, which is located between a first portion of the clip and a first short side of the source pad for main transistor in a plan view.
    Type: Application
    Filed: August 24, 2022
    Publication date: May 11, 2023
    Inventors: Hideki SASAKI, Tatsuaki TSUKUDA, Hiroya SHIMOYAMA
  • Patent number: 11626374
    Abstract: A semiconductor device includes a wiring substrate including a first wiring layer. The first wiring layer includes a first wiring pattern which is a transmission path of a first signal, a second wiring pattern which is a transmission path of a second signal and which is arranged next to one side of the first wiring pattern, and a third wiring pattern which is a transmission path of a third signal and which is arranged next to the other side of the first wiring pattern. A wiring pattern group including the first through third wiring patterns has: a first portion in which wiring widths of the first through third wiring patterns are equal to each other; and a second portion in which the wiring width of the first wiring pattern is larger than the wiring width of each of the second and third wiring patterns.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: April 11, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuaki Tsukuda
  • Patent number: 11617265
    Abstract: A width of each of a first signal terminal and a reference potential terminal formed in a first connection region of a core insulating layer constituting a flexible substrate is larger than a width of each of a first backside signal terminal and a backside reference potential terminal formed in a second connection region of the core insulating layer. In addition, a first separation distance between the first signal terminal and the reference potential terminal arranged adjacent to the first signal terminal is smaller than a second separation distance between the first backside signal terminal and the backside reference potential terminal arranged adjacent to the first backside signal terminal. An insulating film formed on a first surface of the core insulating layer at a position overlapping each of the first connection region and the second connection region covers the first connection region such that the second connection region is exposed.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: March 28, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Tsuchiyama, Tatsuaki Tsukuda
  • Publication number: 20230062318
    Abstract: A performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip, and a clip mounted on the semiconductor chip via a silver paste. Here, the semiconductor chip includes a passivation film having an opening, a source pad of a main transistor having a portion exposed from the passivation film at the opening, and a wall portion provided on the passivation film so as to surround the source pad in a plan view. At this time, a whole of the portion (exposed surface) of the source pad, which is exposed from the passivation film, is covered with the silver paste. Further, in the plan view, the silver paste connecting the source pad with the clip is positioned inside of an area surrounded by the wall portion, without overflowing.
    Type: Application
    Filed: July 25, 2022
    Publication date: March 2, 2023
    Inventor: Tatsuaki TSUKUDA
  • Patent number: 11509220
    Abstract: An electronic device comprises a switching regulator. Here, the switching regulator has a first wiring portion (including a parasitic inductance) coupling the high-side element and the low-side element, and a second wiring portion (including a parasitic inductance) coupled with the low-side element. Also, the switching regulator has a first region in where the first wiring portion and the second wiring portion are lined up with each other. As a result, the performance of the electronic device can be improved.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 22, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuaki Tsukuda
  • Publication number: 20200412245
    Abstract: An electronic device comprises a switching regulator. Here, the switching regulator has a first wiring portion (including a parasitic inductance) coupling the high-side element and the low-side element, and a second wiring portion (including a parasitic inductance) coupled with the low-side element. Also, the switching regulator has a first region in where the first wiring portion and the second wiring portion are lined up with each other. As a result, the performance of the electronic device can be improved.
    Type: Application
    Filed: April 20, 2020
    Publication date: December 31, 2020
    Inventor: Tatsuaki TSUKUDA
  • Patent number: 10811344
    Abstract: An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface. The semiconductor device includes a semiconductor chip on a die pad sealed by a sealing body. A back surface of the die pad is directed to a main surface of the sealing body. A back surface of the sealing body faces the main surface of the wiring board. First and second electrodes are formed on the wiring board and in the sealing body, respectively. The second electrode is disposed in the back surface of the sealing body, and is bonded to a metal plate connecting a lead and a pad. A distance between the first and second electrodes is shorter than that between the metal plate and the first electrode. The first and second electrodes overlap each other in a plan view. A capacitor is composed of the first and second electrodes.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuaki Tsukuda
  • Patent number: 10638600
    Abstract: An electronic device according to one embodiment includes a wiring substrate, the wiring substrate having a first wiring connected to a first external terminal and a second wiring connected to a second external terminal and extending along the first wiring. Additionally, the above electronic device has a semiconductor device mounted on the above wiring substrate and electrically connected to each of the first and second wirings. Further, the above electronic device has a capacitor mounted on the above wiring substrate and electrically connected to the semiconductor device via each of the above first and second wirings. Furthermore, a distance between the above semiconductor device and capacitor is shorter than a distance between each of the above first and second external terminals and the above capacitor.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 28, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuaki Tsukuda, Akihiro Nakahara
  • Publication number: 20190333866
    Abstract: An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface. The semiconductor device includes a semiconductor chip on a die pad sealed by a sealing body. A back surface of the die pad is directed to a main surface of the sealing body. A back surface of the sealing body faces the main surface of the wiring board. First and second electrodes are formed on the wiring board and in the sealing body, respectively. The second electrode is disposed in the back surface of the sealing body, and is bonded to a metal plate connecting a lead and a pad. A distance between the first and second electrodes is shorter than that between the metal plate and the first electrode. The first and second electrodes overlap each other in a plan view. A capacitor is composed of the first and second electrodes.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 31, 2019
    Inventor: Tatsuaki TSUKUDA
  • Patent number: 10205237
    Abstract: A loop antenna 1 includes: a first electrode terminal 2c; a second electrode terminal 2d arranged to make a pair with the first electrode terminal 2c; and a loop-shaped member 2 which has one end connected to the first electrode terminal 2c and the other end connected to the second electrode terminal 2d, is wound a plurality of times, and is made of a conductive material. The first electrode terminal 2c and the second electrode terminal 2d are arranged so as to make a pair with respect to a center line 3 of the loop-shaped member 2. Further, the loop-shaped member 2 includes a first loop-shaped member 2a, a second loop-shaped member 2b, and an intersection part 2e. The intersection part 2e is arranged on the center line 3 in a plan view, and the loop-shaped member 2 is continuously connected and formed to be symmetrical with respect to the center line 3.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuaki Tsukuda, Hideki Sasaki
  • Patent number: 10165673
    Abstract: A wiring board of an electronic device includes: a board terminal connected to a semiconductor device (semiconductor component); a wire formed in a first wiring layer and electrically connected to the board terminal; a conductor pattern formed in a second wiring layer and electrically connected to the wire via a via wire; and another conductor pattern formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern and the another conductor pattern face each other with an insulating layer interposed therebetween, and an area of a region where the conductor pattern and the another conductor pattern face each other is larger than an area of the wire.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 25, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuaki Tsukuda
  • Publication number: 20180295715
    Abstract: An electronic device according to one embodiment includes a wiring substrate, the wiring substrate having a first wiring connected to a first external terminal and a second wiring connected to a second external terminal and extending along the first wiring. Additionally, the above electronic device has a semiconductor device mounted on the above wiring substrate and electrically connected to each of the first and second wirings. Further, the above electronic device has a capacitor mounted on the above wiring substrate and electrically connected to the semiconductor device via each of the above first and second wirings. Furthermore, a distance between the above semiconductor device and capacitor is shorter than a distance between each of the above first and second external terminals and the above capacitor.
    Type: Application
    Filed: November 30, 2015
    Publication date: October 11, 2018
    Inventors: Tatsuaki TSUKUDA, Akihiro NAKAHARA
  • Publication number: 20180263108
    Abstract: A wiring board of an electronic device includes: a board terminal connected to a semiconductor device (semiconductor component); a wire formed in a first wiring layer and electrically connected to the board terminal; a conductor pattern formed in a second wiring layer and electrically connected to the wire via a via wire; and another conductor pattern formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern and the another conductor pattern face each other with an insulating layer interposed therebetween, and an area of a region where the conductor pattern and the another conductor pattern face each other is larger than an area of the wire.
    Type: Application
    Filed: January 12, 2018
    Publication date: September 13, 2018
    Inventor: Tatsuaki TSUKUDA
  • Patent number: 10044195
    Abstract: To achieve a reduction of noise in a wireless system of an electronic device for communication. The electronic device for communication includes: a bottom lid; a loop antenna that forms an electromagnetic field; a communication circuit coupled to the loop antenna; a battery pack that is a metallic part; a magnetic sheet arranged between the loop antenna and the metallic part, the magnetic sheet including a protruding portion that protrudes outside an outer peripheral portion of the loop antenna; a wiring substrate arranged over the battery pack and having an IC and the like mounted thereon; and a lid with a display arranged over the wiring substrate, in which, with the outer peripheral portion of the loop antenna as a base point, a protruding amount from the base point of the protruding portion of the magnetic sheet is twice or more a wiring width of the loop antenna.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuaki Tsukuda, Hideki Sasaki
  • Publication number: 20170207535
    Abstract: A loop antenna 1 includes: a first electrode terminal 2c; a second electrode terminal 2d arranged to make a pair with the first electrode terminal 2c; and a loop-shaped member 2 which has one end connected to the first electrode terminal 2c and the other end connected to the second electrode terminal 2d, is wound a plurality of times, and is made of a conductive material. The first electrode terminal 2c and the second electrode terminal 2d are arranged so as to make a pair with respect to a center line 3 of the loop-shaped member 2. Further, the loop-shaped member 2 includes a first loop-shaped member 2a, a second loop-shaped member 2b, and an intersection part 2e. The intersection part 2e is arranged on the center line 3 in a plan view, and the loop-shaped member 2 is continuously connected and formed to be symmetrical with respect to the center line 3.
    Type: Application
    Filed: July 30, 2014
    Publication date: July 20, 2017
    Inventors: Tatsuaki TSUKUDA, Hideki SASAKI
  • Patent number: 9705363
    Abstract: In a communication control device in which an antenna electrode having an antenna connected thereto, a power supply circuit, and a communication circuit are mounted on a mounting board, the antenna electrode is disposed at one corner portion on a principal surface of the mounting board, the communication circuit is disposed on a side of a first side of the principal surface that shares the corner portion, and the power supply circuit is disposed on a side of a second side facing the first side. Further, a first signal path connecting the antenna electrode and the communication circuit extends along the first side, and a second signal path connecting the antenna electrode and the power supply circuit extends along a third side that shares the corner portion and is perpendicular to the first side.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: July 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroki Shibuya, Hideki Sasaki, Tatsuaki Tsukuda, Tadashi Shimizu, Masahiro Dobashi, Shinji Nishizono, Hiroko Kubota
  • Publication number: 20160156231
    Abstract: In a communication control device in which an antenna electrode having an antenna connected thereto, a power supply circuit, and a communication circuit are mounted on a mounting board, the antenna electrode is disposed at one corner portion on a principal surface of the mounting board, the communication circuit is disposed on a side of a first side of the principal surface that shares the corner portion, and the power supply circuit is disposed on a side of a second side facing the first side. Further, a first signal path connecting the antenna electrode and the communication circuit extends along the first side, and a second signal path connecting the antenna electrode and the power supply circuit extends along a third side that shares the corner portion and is perpendicular to the first side.
    Type: Application
    Filed: June 14, 2013
    Publication date: June 2, 2016
    Inventors: Hiroki SHIBUYA, Hideki SASAKI, Tatsuaki TSUKUDA, Tadashi SHIMIZU, Masahiro DOBASHI, Shinji NISHIZONO, Hiroko KUBOTA
  • Publication number: 20160064823
    Abstract: To achieve a reduction of noise in a wireless system of an electronic device for communication. The electronic device for communication includes: a bottom lid; a loop antenna that forms an electromagnetic field; a communication circuit coupled to the loop antenna; a battery pack that is a metallic part; a magnetic sheet arranged between the loop antenna and the metallic part, the magnetic sheet including a protruding portion that protrudes outside an outer peripheral portion of the loop antenna; a wiring substrate arranged over the battery pack and having an IC and the like mounted thereon; and a lid with a display arranged over the wiring substrate, in which, with the outer peripheral portion of the loop antenna as a base point, a protruding amount from the base point of the protruding portion of the magnetic sheet is twice or more a wiring width of the loop antenna.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Inventors: Tatsuaki Tsukuda, Hideki Sasaki