Patents by Inventor Tatsuji Nagaoka
Tatsuji Nagaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7067877Abstract: A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base region, a gate insulation film on the base region, a gate electrode on the gate insulation film, an oxide film on the drift region, a field plate on the oxide film, and a source electrode. The position (P) of the impurity concentration peak in base region is located more closely to the drift region. The oxide film is thinner on the side of the gate electrode. The field plate is connected electrically to the source electrode, the spacing (dg) between the gate insulation film and the stopper region is 2.5 ?m or narrower, and the minimum spacing (x) between the drain region and the stopper region is 5.6 ?m or narrower.Type: GrantFiled: February 18, 2004Date of Patent: June 27, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Tatsuji Nagaoka
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Patent number: 7042046Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: GrantFiled: August 25, 2004Date of Patent: May 9, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20060086998Abstract: The semiconductor apparatus is disclosed that includes a partial SOI substrate including an oxide film; a lateral first MOSFET section having a planar gate structure and formed in the portion of the partial SOI substrate where there is an oxide film; a vertical second MOSFET section having a trench gate structure and formed in the portion of the partial SOI substrate where there is no oxide film, the second MOSFET section being adjacent to the first MOSFET section. The first MOSFET section includes a first p-type base region on the oxide film. The second MOSFET section includes a second n+-type drain region, a second n-type drift region on the second n+-type drain region, and a second p-type base region in the surface portion of the second n-type drift region.Type: ApplicationFiled: September 15, 2005Publication date: April 27, 2006Applicant: Fuji Electric Holdings Co., Ltd.Inventor: Tatsuji Nagaoka
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Patent number: 7002205Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: GrantFiled: December 12, 2003Date of Patent: February 21, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
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Patent number: 6924727Abstract: A security system 63 and an electronic device group 62 to be stored in a home network 6 are controlled by a home server 61. A home network management facility 5 obtains status information of the electronic device group 62 from home server 61. Home network management facility 5 displays the status of electronic device group 62 on a display unit of a terminal 1 based on the received status information. Home network management facility 5 also displays a screen for prompting input of a control instruction of the home-located electronic devices that are included in the electronic device group 62. Based on control instruction received via home server 61, home network management facility 5 performs remote control of electronic device group 62.Type: GrantFiled: September 27, 2001Date of Patent: August 2, 2005Assignee: NTT DoCoMo, Inc.Inventors: Tatsuji Nagaoka, Kazuo Nomura, Yutaka Hiruma
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Patent number: 6903418Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.Type: GrantFiled: October 3, 2003Date of Patent: June 7, 2005Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20050098846Abstract: A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base region, a gate insulation film on the base region, a gate electrode on the gate insulation film, an oxide film on the drift region, a field plate on the oxide film, and a source electrode. The position (P) of the impurity concentration peak in base region is located more closely to the drift region. The oxide film is thinner on the side of the gate electrode. The field plate is connected electrically to the source electrode, the spacing (dg) between the gate insulation film and the stopper region is 2.5 ?m or narrower, and the minimum spacing (x) between the drain region and the stopper region is 5.6 ?m or narrower.Type: ApplicationFiled: February 18, 2004Publication date: May 12, 2005Inventor: Tatsuji Nagaoka
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Publication number: 20050017292Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: ApplicationFiled: August 25, 2004Publication date: January 27, 2005Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
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Patent number: 6825537Abstract: In a trench super junction semiconductor element having a parallel p-n junction layer 14 with n-drift regions 12 and p-partition regions 13, both extending in a depth direction, being alternately joined, a part 20 in a shape of a three-dimensional curved surface in the end portion of each of trenches is formed in a p-partition region 13. A section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface of the end portion of each of the trenches is made as a p+-region 21 in which an impurity concentration is higher than that in a section thereunder so that an electric field is increased at a boundary between the p+-region 21 and the n-drift region 12, thereby lessening electric field concentration to the part 20 in a shape of a three-dimensional curved surface of the end portion of the trench.Type: GrantFiled: October 10, 2003Date of Patent: November 30, 2004Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Susumu Iwamoto, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
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Patent number: 6825565Abstract: A semiconductor device includes a drift region, which includes a first alternating conductivity type layer, and a peripheral region, which includes a second alternating conductivity type layer and a third alternating conductivity type layer in the surface portion of the peripheral region. The first layer includes first n-type regions and first p-type regions arranged alternately at a first pitch. The second layer is continuous with the first layer and includes second n-type regions and second p-type regions arranged alternately at the first pitch. The impurity concentration in the second layer is almost the same as the impurity concentration in the first layer. The third layer includes third n-type regions and third p-type regions arranged alternately at a second pitch. The third layer can be doped more lightly than the first and second alternating conductivity type layers. The second pitch can be the same as the first pitch or smaller.Type: GrantFiled: January 30, 2003Date of Patent: November 30, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuji Nagaoka, Susumu Iwamoto, Takahiro Sato
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Patent number: 6768167Abstract: A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using the gate electrode as a mask to form a second drain region, which also serves as a drift region.Type: GrantFiled: May 21, 2003Date of Patent: July 27, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Tatsuji Nagaoka, Tatsuhiko Fujihira, Yasuhiko Onishi
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Publication number: 20040135228Abstract: In a trench super junction semiconductor element having a parallel p-n junction layer 14 with n-drift regions 12 and p-partition regions 13, both extending in a depth direction, being alternately joined, a part 20 in a shape of a three-dimensional curved surface in the end portion of each of trenches is formed in a p-partition region 13. A section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface of the end portion of each of the trenches is made as a p+-region 21 in which an impurity concentration is higher than that in a section thereunder so that an electric field is increased at a boundary between the p+-region 21 and the n-drift region 12, thereby lessening electric field concentration to the part 20 in a shape of a three-dimensional curved surface of the end portion of the trench.Type: ApplicationFiled: October 10, 2003Publication date: July 15, 2004Inventors: Susumu Iwamoto, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20040124465Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: ApplicationFiled: December 12, 2003Publication date: July 1, 2004Applicant: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20040088736Abstract: The object of the present invention is to provide a contents providing system which can give an incentive to audiences to view the broadcast program, by providing contents information from a broadcast station apparatus to a mobile terminal via a television set, and the mobile terminal which can be used in the contents providing system. The broadcast station apparatus 50 comprises a multiplexing signal transmitter 53 and 54 configured to transmit a multiplexing signal multiplexing broadcast program information and contents information. The television set 30 comprises a separator 32 configured to separate the broadcast program information and the contents information from the received multiplexing signal, a reproducer 33 configured to reproduce the broadcast program information, and a transmitter 35 configured to transmit the contents information to the mobile terminal during the reproducing of the broadcast program information.Type: ApplicationFiled: October 2, 2003Publication date: May 6, 2004Applicant: NTT DoCoMo, IncInventors: Tatsuji Nagaoka, Kazuo Nomura
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Patent number: 6724042Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.Type: GrantFiled: February 9, 2001Date of Patent: April 20, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20040065921Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.Type: ApplicationFiled: October 3, 2003Publication date: April 8, 2004Applicant: Fuji Electric Co., Ltd.Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20040056284Abstract: A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using the gate electrode as a mask to form a second drain region, which also serves as a drift region.Type: ApplicationFiled: May 21, 2003Publication date: March 25, 2004Inventors: Tatsuji Nagaoka, Tatsuhiko Fujihira, Yasuhiko Onishi
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Patent number: 6696728Abstract: To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.Type: GrantFiled: March 15, 2002Date of Patent: February 24, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
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Patent number: 6674126Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.Type: GrantFiled: February 11, 2002Date of Patent: January 6, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
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Publication number: 20030176031Abstract: A semiconductor device includes a drift region, which includes a first alternating conductivity type layer, and a peripheral region, which includes a second alternating conductivity type layer and a third alternating conductivity type layer in the surface portion of the peripheral region. The first layer includes first n-type regions and first p-type regions arranged alternately at a first pitch. The second layer is continuous with the first layer and includes second n-type regions and second p-type regions arranged alternately at the first pitch. The impurity concentration in the second layer is almost the same as the impurity concentration in the first layer. The third layer includes third n-type regions and third p-type regions arranged alternately at a second pitch. The third layer can be doped more lightly than the first and second alternating conductivity type layers. The second pitch can be the same as the first pitch or smaller.Type: ApplicationFiled: January 30, 2003Publication date: September 18, 2003Inventors: Yasuhiko Onishi, Tatsuji Nagaoka, Susumu Iwamoto, Takahiro Sato