Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.

Abstract: According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.

Abstract: According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

Abstract: A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power.

Abstract: According to an embodiment, a control apparatus for controlling a target device includes an estimation unit and an issuing unit. The estimation unit is configured to estimate a second amount of energy required for the entire system including the target device and the control apparatus until the target device completes an execution of its function that is requested in accordance with an execution request for the target device. The issuing unit is configured to issue a control command for causing the target device to execute its function in accordance with the execution request, when the first amount of energy at a time point of receiving the execution request is greater than the second amount of energy.

Abstract: According to an embodiment, an electronic device includes functional modules and converters. A processor includes a memory storing state information on the state of the processor. Each converter converts the power-supply voltage to a rated voltage for functional modules, and supplies the rated voltage to at least one functional module. When the processor switches to the standby state, a controller stops the supply of the rated voltages to the functional modules except a state holding unit, a receiving unit, and the controller; and stops the operations of the converters not connected to the state holding unit, the receiving unit, and the controller. The state holding unit holds the state information before the processor switches to the standby state. The receiving unit receives a return signal representing the trigger for returning from the standby state. The state holding unit, the receiving unit, and the controller are connected to the same converter.

Abstract: According to an embodiment, in an information processing device, when there is no change in a first image received from an image sensor, reception of the next first image is awaited. When there is a change in the first image, a second image having a higher resolution than the first image is received from the image sensor and processing for the second image is performed.

Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.

Abstract: According to a power system includes a linear regulator, a step-down switching regulator, and a controller. The linear regulator supplies electrical power to a load. The step-down switching regulator supplies electrical power to the load. Based on input voltage of the linear regulator and the step-down switching regulator and based on load current representing electrical current flowing to the load, the controller performs control to supply electrical power to the load from one of the linear regulator and the switching regulator.

Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.

Abstract: A memory system comprises an encoding processing circuit 100 that performs redundant encoding process on target data Din to be written to thereby generate data RDin such that the number of bits having a predetermined value is half or less than the total number of bits, and a memory 120 to which the data RDin generated by the encoding processing circuit are written.

Abstract: According to an embodiment, a communication device for dynamically building a network includes a first receiver and a first transmitter. When the communication device attempts to newly join the network, the first receiver waits for reception of a first beacon containing information for joining the network from another communication device already joining the network for a predetermined first period. When the communication device is already joining the network, the first transmitter determines a schedule indicating timings at which a plurality of communication devices already joining the network transmit first beacons so that intervals at which the communication devices transmit the first beacons in the network as a whole do not exceed the first period and transmit the first beacon according to the schedule.

Abstract: According to an embodiment, a communication device includes a register and a controller. The register receives data from an external device via an input data line. In a first state in which the communication device is able to receive the data, when a condition in which the data is not sent to the input data line continues for a certain period of time, the controller controls to switch state of the communication device to a second state in which power consumption is less than in the first state.

Abstract: According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value.

Abstract: According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.

Abstract: A data processing device according to embodiments may comprise: a processor that reconstructs a plurality of update requests for updating at least a part of a display into one or more update requests, or determine that the plurality of the update requests are unnecessary; and an update instruction unit that instructs to execute update processes of the display using the reconstructed one or more update requests.

Abstract: In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.

Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.

Abstract: According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.