Patents by Inventor Tatsunori Sakano

Tatsunori Sakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273134
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating portion. The first semiconductor region includes first to third partial regions. The first partial region is provided between the first electrode and the second electrode. The second partial region is provided between the first and third electrodes. The second semiconductor region includes fourth to sixth partial regions. The fourth partial region is provided between the first partial region and the second electrode. The fifth partial region is provided between the third semiconductor region and at least a portion of the second partial region. The sixth partial region is provided between the third partial region and the third semiconductor region. The fourth semiconductor region is provided between the first and fourth partial regions. The first insulating portion is provided between the second partial region and the third electrode.
    Type: Application
    Filed: August 10, 2018
    Publication date: September 5, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chiharu Ota, Tatsunori Sakano, Ryosuke Iijima
  • Patent number: 9640718
    Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: May 2, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Miura, Tatsunori Sakano, Tomomasa Ueda, Nobuyoshi Saito, Shintaro Nakano, Yuya Maeda, Hajime Yamaguchi
  • Patent number: 9614099
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Masaki Atsuta, Hajime Yamaguchi
  • Publication number: 20160378249
    Abstract: According to an embodiment, an input device includes the following elements. The flexible touch panel includes a sensor area. The touch position detector detects a touch position on the sensor area to generate a detection signal. The deformation position detector detects a deformation position where a deformation amount is not less than a threshold on the sensor area. The input rejection area determination unit determines, based on the deformation position, an input rejection area. The input signal generator fails to output the detection signal as an input signal if the touch position is detected in the input rejection area, and outputs the detection signal as an input signal if the touch position is detected in an area other than the input rejection area.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MIURA, Hajime YAMAGUCHI, Tatsunori SAKANO, Tomomasa UEDA, Nobuyoshi SAITO, Shintaro NAKANO
  • Patent number: 9324879
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 9293600
    Abstract: A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Masaki Atsuta, Hajime Yamaguchi
  • Patent number: 9224871
    Abstract: According to one embodiment, a thin film transistor includes a first insulating film, a gate electrode, a semiconductor layer, a gate insulator film, a second insulating film, a source electrode, a tunneling insulating portion, and a drain electrode. The semiconductor layer is provided between the gate electrode and the first insulating film, and includes an amorphous oxide. The gate insulator film is provided between the semiconductor layer and the gate electrode. The second insulating film is provided between the semiconductor layer and the first insulating film. The tunneling insulating portion is provided between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode, and between the first insulating film and the second insulating film. The tunneling insulating portion includes oxygen and at least one selected from aluminum and magnesium. A thickness of the tunneling insulating portion is 2 nanometers or less.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuya Maeda, Hajime Yamaguchi, Tomomasa Ueda, Kentaro Miura, Shintaro Nakano, Nobuyoshi Saito, Tatsunori Sakano
  • Publication number: 20150372147
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Application
    Filed: August 27, 2015
    Publication date: December 24, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Tomomasa UEDA, Kentaro MIURA, Nobuyoshi SAITO, Tatsunori SAKANO, Hajime YAMAGUCHI
  • Patent number: 9204554
    Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Sakano, Kentaro Miura, Nobuyoshi Saito, Shintaro Nakano, Tomomasa Ueda, Hajime Yamaguchi
  • Patent number: 9184408
    Abstract: According to one embodiment, a display panel includes a substrate, a switching element, a pixel electrode, an organic light emitting layer, an opposite electrode, a detecting electrode, and an insulating layer. The substrate has a major surface. The switching element is provided on the major surface. The switching element includes a semiconductor layer. The pixel electrode is provided on the major surface. The pixel electrode is electrically connected to the switching element. The organic light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the organic light emitting layer. The detecting electrode is provided between the substrate and at least a part of the pixel electrode. The detecting electrode includes at least one element included in the semiconductor layer. The insulating layer is provided between the pixel electrode and the detecting electrode.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano
  • Patent number: 9159747
    Abstract: According to one embodiment, a display device includes a substrate unit, a thin film transistor, a pixel electrode and a display layer. The substrate unit includes a substrate, a first insulating layer provided on the substrate, and a second insulating layer provided on the first insulating layer. The thin film transistor is provided on the substrate unit and includes a gate electrode provided on the second insulating layer, a semiconductor layer of an oxide separated from the gate electrode, a gate insulation layer provided between the gate electrode and the semiconductor layer, a first conductive portion, a second conductive portion, and a third insulating layer. The pixel electrode is connected to one selected from the first and second conductive portions. The display layer is configured to have a light emission or a change of optical characteristic occurring according to a charge supplied to the pixel electrode.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Hajime Yamaguchi
  • Patent number: 9159836
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 9029853
    Abstract: According to one embodiment, a display device includes a first insulating layer, a second insulating layer, a pixel electrode, a light emitting layer, an opposite electrode and a pixel circuit. The second insulating layer is provided on the first insulating layer. The pixel electrode is provided on the second insulating layer and light-transmissive. The light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the light emitting layer. The circuit is provided between the first insulating layer and the second insulating layer, includes an interconnect supplied with a drive current, and is configured to supply the drive current to the pixel electrode. The circuit is connected to the pixel electrode. The interconnect has a first region overlaying the pixel electrode when projected onto a plane parallel to the first insulating layer. The interconnect has an opening in the first region.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Toshiya Yonehara, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano
  • Patent number: 9006828
    Abstract: A display device includes a first electrode, a second electrode, an organic light emitting layer, a first transistor, and a second transistor. The first transistor includes a first semiconductor layer, a first conductive unit, a second conductive unit, a first gate electrode, and a first gate insulating film. The second transistor includes a second semiconductor layer, a third conductive unit, a fourth conductive unit, a second gate electrode, and a second gate insulating film. An amount of hydrogen included in the first gate insulating film is larger than an amount of hydrogen included in the second gate insulating film.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Yuya Maeda, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 8994020
    Abstract: According to one embodiment, a display device includes a thin film transistor. The thin film transistor includes a gate insulating film, a semiconductor layer, a gate electrode, first and second channel protection films, first and second conductive layers, and a passivation film. The semiconductor layer is provided on a major surface of the gate insulating film. The semiconductor layer includes first to seventh portions. The gate insulating film is disposed between the semiconductor layer and the gate electrode. The first channel protection film covers the third portion. The second channel protection film covers the fifth and fourth portions, and an upper surface of the first channel protection film. The first conductive layer covers the sixth portion. The second conductive layer covers the seventh portion. The passivation film covers the first and second portions, the first and second conductive layers, and the second channel protection film.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Tomomasa Ueda, Hajime Yamaguchi
  • Publication number: 20150084040
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.
    Type: Application
    Filed: August 8, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Tomomasa UEDA, Kentaro MIURA, Nobuyoshi SAITO, Tatsunori SAKANO, Yuya MAEDA, Masaki ATSUTA, Hajime YAMAGUCHI
  • Publication number: 20150087093
    Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. The method can include forming a first resin layer on a substrate. The method can include forming a display layer on the first resin layer. The display layer includes a plurality of pixels arranged in a direction perpendicular to a stacking direction of the first resin layer and the display layer. Each of the pixels includes a first electrode provided on the first resin layer, an organic light emitting layer provided on the first electrode, and a second electrode provided on the organic light emitting layer. The method can include bonding a second resin layer onto the display layer via a bonding layer. The method can include removing the substrate. The method can include increasing a density of the bonding layer.
    Type: Application
    Filed: August 13, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori SAKANO, Kentaro Miura, Tomomasa Ueda, Nobuyoshi Saito, Shintaro Nakano, Yuya Maeda, Hajime Yamaguchi
  • Publication number: 20150084042
    Abstract: According to one embodiment, a thin film transistor includes a first insulating film, a gate electrode, a semiconductor layer, a gate insulator film, a second insulating film, a source electrode, a tunneling insulating portion, and a drain electrode. The semiconductor layer is provided between the gate electrode and the first insulating film, and includes an amorphous oxide. The gate insulator film is provided between the semiconductor layer and the gate electrode. The second insulating film is provided between the semiconductor layer and the first insulating film. The tunneling insulating portion is provided between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode, and between the first insulating film and the second insulating film. The tunneling insulating portion includes oxygen and at least one selected from aluminum and magnesium. A thickness of the tunneling insulating portion is 2 nanometers or less.
    Type: Application
    Filed: August 22, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuya MAEDA, Hajime YAMAGUCHI, Tomomasa UEDA, Kentaro MIURA, Shintaro NAKANO, Nobuyoshi SAITO, Tatsunori SAKANO
  • Publication number: 20150084021
    Abstract: A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion.
    Type: Application
    Filed: August 18, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Tomomasa UEDA, Kentaro MIURA, Nobuyoshi SAITO, Tatsunori SAKANO, Yuya MAEDA, Masaki ATSUTA, Hajime YAMAGUCHI
  • Patent number: 8987712
    Abstract: According to one embodiment, a display device includes a light transmissive substrate, a light transmissive pixel electrode, a switching element, an organic light emitting layer, a light transmissive opposite electrode, a conductive light absorption layer and a conductive film. The light transmissive pixel electrode is provided on the substrate. The switching element is provided on the substrate and electrically connected to the pixel electrode. The organic light emitting layer is provided on the pixel electrode. The light transmissive opposite electrode is provided on the organic light emitting layer. The conductive light absorption layer is provided on the opposite electrode. The conductive film is provided on the light absorption layer.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Kentaro Miura, Tomomasa Ueda, Shintaro Nakano, Tatsunori Sakano, Hajime Yamaguchi