Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, the heat diffusion characteristic and the device performance in high-speed operation, and, therefor, in a group III nitride semiconductor device of the present invention, an epitaxial growth layer 13 of a group III nitride semiconductor with a buffer layer 12 laid under it is formed on a sapphire substrate 11 in which an A plane (an (11-20) plane) is set to be the principal plane, and thereon a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed, wherein a thickness of the single crystalline sapphire substrate is specifically set to be 100 &mgr;m or less.

Abstract: A fuel cell system and a method of operating the system capable of increasing the service life of an ion exchange resin used for maintaining the water quality of cooling water and reducing the power consumption of auxiliary equipment at a low cost by avoiding a pressure variation in a cooling water channel; the fuel cell system, comprising a solid high polymer fuel cell (11), a cooling water tank (12), a cooling water channel (13), a cooling water pump (14), a heat exchanger (15), a fuel side condenser (16) and an air side condenser (17) for cooling the exhaust fuel gas and exhaust oxidizer gas exhausted from the fuel cell (11) to condensate the vapor contained therein, a condensed water tank (18) for storing the water condensed by the fuel side condenser (16) and the air side condenser (17), a water feed passage (20) having a water feed pump (19) for feeding the condensed water to the cooling water tank (12) provided therein, and a water drain passage (21) from the cooling water tank (12).

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Abstract: In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At least a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

Abstract: A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Abstract: An FET (Field Effect Transistor) includes a substrate. Sequentially formed on the substrate area buffer layer (200 nm thick) formed of a first sphalerite type semiconductor implemented by In0.52Al0.48, a carrier running layer (6 nm thick) formed of a second sphalerite type semiconductor implemented by In0.53Ga0.47As, an InAs carrier running layer (7 nm thick), an AlAs spacer layer (2 nm thick), a spacer layer (2 nm thick) formed of a third sphalerite type semiconductor implemented by In0.52Al0.48As, a carrier supply layer (20 nm thick) formed of a fourth sphalerite type semiconductor implemented by n−In0.52Al0.48As with 3×1018 cm−3 of Si added thereto, a Schottky layer (15 nm thick) formed of a fifth sphalerite type semiconductor implemented by In0.52Al0.48As, and a cap layer (20 nm thick) formed of a sixth sphalerite type semiconductor implemented by n-In0.53Ga0.47As with 1×1019 cm−3 of Si added thereto.

Abstract: In an InAlAs/InGaAs heterojunction field type semiconductor device including an InP substrate, a superlattice layer formed by periods of InAs/AlAs or InAs/AlGaAs is formed over an InGaAs channel layer which is formed over the InP substrate.

Abstract: A heterojunction field effect transistor having an InP substrate, comprising a buffer layer formed between an active layer where a carrier travels and said InP substrate, wherein said buffer layer has at least two cycles of superlattices, each of said superlattices being formed of at least one semiconductor selected from the group consisting of Al.sub.x In.sub.1-x P (0.1.ltoreq.x.ltoreq.1), Ga.sub.x In.sub.1-x P (0.ltoreq.x.ltoreq.1), Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1), and Al.sub.x In.sub.1-x As (0.5.ltoreq.x.ltoreq.1), and at least one semiconductor selected from the group consisting of InP and In.sub.0.52 Al.sub.0.48 As.

Abstract: A semiconductor device that enables to prevent the electron transport property of a semiconductor active layer from degrading even if a semiconductor compositionally-graded buffer layer is used. This device contains a semiconductor substrate, a semiconductor active layer lattice-mismatched with the substrate, and a semiconductor compositionally-graded buffer layer formed between the substrate and the active layer. The compositionally-graded buffer layer has a semiconductor superlattice structure including first semiconductor sublayers and second semiconductor sublayers that are alternately stacked in a direction perpendicular to the substrate. Each of the first sublayers is made of a first semiconductor material. Each of the second sublayers is made of a second semiconductor material different in composition from the first semiconductor material. The lattice constant of the first and second sublayers decreases or increases stepwise from a side near the substrate and the other side near the active layer.

Abstract: An active layer of a field effect transistor disposed on an InP substrate (101) comprises at least an InAs layer (105) and two InGaAs layers (104, 106). The InGaAs layer (104) is In.sub.x Ga.sub.1-x As (wherein 0.55<x<1) and the InGaAs layer (106) is In.sub.y Ga.sub.1-y As (wherein 0.55<y<1). The active layer comprises, for example, In.sub.0.53 Ga.sub.0.47 As layer (103)/In.sub.0.8 Ga.sub.0.2 As layer (104)/InAs layer (105)/In.sub.0.8 Ga.sub.0.2 As layer (106)/In.sub.0.53 Ga.sub.0.47 As layer (107). Electrons which have been leached out of the InAs layer (105) are confined into the InGaAs layers (104, 106), and about 90% of the active electrons are accumulated in the layers (104, 105, 106) to achieve an excellent electron transport performance, so that an excellent high frequency characteristic can be obtained exhibiting a high cut-off frequency and an improved transconductance.

Abstract: The present invention relates to a field effect transistor with high speed and excellent high frequency characteristics. A hetero junction field effect transistor, comprising a first semiconductor layer that contains In, a second semiconductor layer that contains In whose composition ratio is smaller than that of the first semiconductor layer, and a third semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are successively disposed in the order, and wherein the thickness of the second semiconductor layer is equal to or larger than the thickness of two monolayers thereof and less than 4 nm. A current of this field effect transistor flows in the first semiconductor layer 3 and the second semiconductor layer 4 of the transistor.

Abstract: An adjustable torque ratchet wrench has a ratchet gear to be meshed with a ratchet pawl that restrains movement of the ratchet gear when a handle is rotated. The ratchet gear includes a shaft connected to a removeable fitting for engaging a bolt or the like to be tightened. The ratchet pawl is mounted on a moveable ratchet pawl block. The ratchet pawl block and the ratchet pawl are urged toward the ratchet gear by an adjustable spring assembly. The user selects a limiting torque using an adjustment means. When the limiting torque is achieved, the force of the spring is overcome and the ratchet pawl disengages from the ratchet gear as the ratchet pawl block slides in the direction of the spring. No further tightening of the bolt may then take place. Embodiments disclosed use varied spring types including disc springs, flat springs, coil springs, loop springs and a series of flat, overlapping springs.

Abstract: A thermoplastic rubber composition comprising a nitrile rubber containing not less than 20% by weight of a gel insoluble in methyl ethyl ketone, a vinyl chloride resin containing 0.05 to 20% by weight of a carboxyl group, a compound of a monovalent or divalent metal and a plasticizer, said monovalent or divalent metal compound being an ionic crosslinking agent which reacts ionically with the carboxyl group of the vinyl chloride resin to crosslink the vinyl chloride resin.