Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract: The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0?x?1), a channel layer composed of InyGa1-yN (0?y?1) with compressive strain and a contact layer composed of AlzGa1-zN (0?z?1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.

Abstract: A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided.

Abstract: Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4.

Abstract: Object of the invention is to reduce the on resistance between source and drain of a nitride semiconductor device. Between a nitride semiconductor layer lying between source and drain regions and a nitride semiconductor layer serving as an underlying layer, formed is a material having an electron affinity greater than that of these nitride semiconductor layers and having a lattice constant greater than that of the nitride semiconductor layer serving as an underlying layer. As a result, an electron density distribution of a channel formed below a gate insulating film and that of a two-dimensional electron gas formed in a region other than the gate portion, when a gate voltage is applied, can be made closer in the depth direction, leading to reduction in on resistance.

Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

Abstract: There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

Abstract: A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0?y?1, 0?z?1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.

Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.

Abstract: A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21?, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25?, wherein the first n-type semiconductor layer 21?, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25? are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21? and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25?.

Abstract: The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

Abstract: The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the lattice-relaxed channel layer 113, and the barrier layer 114 having a tensile strain, and the spacer layer 115 are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

Abstract: A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2?) is formed on a substrate (1?). A p-type conductive layer (3?) is formed thereon. A second n-type conductive layer (4?) is formed thereon. On the under surface of the substrate (1?), there is a drain electrode (13?) connected to the first n-type conductive layer (2?). On the upper surface of the substrate (1?), there is a source electrode (11?) in ohmic contact with the second n-type conductive layer (4?), and a gate electrode (12?) in contact with the first n-type conductive layer (2?), p-type conductive layer (3?), the second n-type conductive layer (4?) through an insulation film (21?). The gate electrode (12?) and the source electrode (11?) are alternately arranged. The p-type conductive layer (3?) includes In.

Abstract: Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.

Abstract: A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0?xc?1, 0?yc?1, 0<xc+yc?1). In the first nitride semiconductor, a length of an a-axis on a surface side is longer than a length of an a-axis on a substrate side.

Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization.

Abstract: A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0?x?1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0?y?1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.

Abstract: Object of the invention is to reduce the on resistance between source and drain of a nitride semiconductor device. Between a nitride semiconductor layer lying between source and drain regions and a nitride semiconductor layer serving as an underlying layer, formed is a material having an electron affinity greater than that of these nitride semiconductor layers and having a lattice constant greater than that of the nitride semiconductor layer serving as an underlying layer. As a result, an electron density distribution of a channel formed below a gate insulating film and that of a two-dimensional electron gas formed in a region other than the gate portion, when a gate voltage is applied, can be made closer in the depth direction, leading to reduction in on resistance.

Abstract: Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4.

Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.