Patents by Inventor Tatsuo Nishita
Tatsuo Nishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11676847Abstract: A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.Type: GrantFiled: October 17, 2022Date of Patent: June 13, 2023Assignee: Tokyo Electron LimitedInventors: Satoshi Taga, Naoyuki Satoh, Tatsuo Nishita
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Publication number: 20230065448Abstract: A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.Type: ApplicationFiled: October 17, 2022Publication date: March 2, 2023Applicant: Tokyo Electron LimitedInventors: Satoshi TAGA, Naoyuki SATOH, Tatsuo NISHITA
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Patent number: 11508603Abstract: A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.Type: GrantFiled: November 23, 2021Date of Patent: November 22, 2022Assignee: Tokyo Electron LimitedInventors: Satoshi Taga, Naoyuki Satoh, Tatsuo Nishita
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Publication number: 20220084867Abstract: A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Applicant: Tokyo Electron LimitedInventors: Satoshi TAGA, Naoyuki SATOH, Tatsuo NISHITA
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Patent number: 11217470Abstract: A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.Type: GrantFiled: December 19, 2019Date of Patent: January 4, 2022Assignee: Tokyo Electron LimitedInventors: Satoshi Taga, Naoyuki Satoh, Tatsuo Nishita
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Publication number: 20200211885Abstract: A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.Type: ApplicationFiled: December 19, 2019Publication date: July 2, 2020Applicant: Tokyo Electron LimitedInventors: Satoshi TAGA, Naoyuki SATOH, Tatsuo NISHITA
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Patent number: 8569186Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.Type: GrantFiled: November 13, 2012Date of Patent: October 29, 2013Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
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Patent number: 8366953Abstract: A plasma cleaning method is performed in a plasma CVD apparatus for depositing a silicon nitride film on a surface of a target substrate, and includes a stage (S1) of supplying a cleaning gas containing NF3 gas into a process container, thereby removing extraneous deposits formed on portions inside the process container; a stage (S2) of supplying a gas containing hydrogen gas into the process container and generating plasma thereof, thereby removing residual fluorine inside the process container; and a stage (S3) of supplying a gas containing a rare gas into the process container and generating plasma thereof, thereby removing residual hydrogen inside the process container.Type: GrantFiled: September 18, 2007Date of Patent: February 5, 2013Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
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Patent number: 8329596Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.Type: GrantFiled: March 19, 2012Date of Patent: December 11, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
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Patent number: 8318614Abstract: A Plasma processing apparatus (100) introduces microwaves into a chamber (1) by a plane antenna (31) which has a plurality of holes. A material gas, which contains a nitrogen-containing compound and a silicon-containing compound, is introduced into the chamber (1) by using the plasma processing apparatus, and plasma is generated by the microwaves. Then, a silicon nitride film is deposited by the plasma on a surface of an object to be processed. The trap density of the silicon nitride film is controlled by adjusting the conditions of the plasma CVD process.Type: GrantFiled: March 25, 2008Date of Patent: November 27, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi, Yoshihiro Hirota
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Patent number: 8258571Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.Type: GrantFiled: June 20, 2008Date of Patent: September 4, 2012Assignees: Tokyo Electron Limited, Tohoku UniversityInventors: Tetsuo Endoh, Masayuki Kohno, Tatsuo Nishita, Minoru Honda, Toshio Nakanishi, Yoshihiro Hirota
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Publication number: 20120184107Abstract: In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O(1D2) radicals produced using a processing gas that contains oxygen are dominant.Type: ApplicationFiled: September 29, 2010Publication date: July 19, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Yoshihiro Sato, Toshihiko Shiozawa, Tatsuo Nishita, Yoshihiro Hirota
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Publication number: 20120178268Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Masayuki KOHNO, Tatsuo NISHITA, Toshio NAKANISHI
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Patent number: 8138103Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.Type: GrantFiled: May 30, 2007Date of Patent: March 20, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
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Patent number: 8119545Abstract: Provided is a plasma CVD device. In the plasma CVD device, in producing a silicon nitride film while controlling the size of a band gap by CVD, microwaves are introduced into a treatment vessel by a flat antenna having a plurality of holes. The plasma CVD is carried out under a given treatment pressure selected from a pressure range of not less than 0.1 Pa and not more than 1333 Pa at a flow ratio between a silicon-containing compound gas and a nitrogen gas (silicon-containing compound gas flow rate/nitrogen gas flow rate) selected from a range of not less than 0.005 and not more than 0.2, whereby the Si/N ratio in the film is controlled to form a silicon nitride film having a band gap size of not less than 2.5 eV and not more than 7 eV.Type: GrantFiled: March 30, 2009Date of Patent: February 21, 2012Assignee: Tokyo Electron LimitedInventors: Minoru Honda, Toshio Nakanishi, Masayuki Kohno, Tatsuo Nishita, Junya Miyahara
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Patent number: 8114790Abstract: A plasma processing apparatus includes a process chamber configured to be vacuum-exhausted; a worktable configured to place a target substrate thereon inside the process chamber; a microwave generation source configured to generate microwaves; a planar antenna including a plurality of slots and configured to supply microwaves generated by the microwave generation source through the slots into the process chamber; a gas supply mechanism configured to supply a film formation source gas into the process chamber; and an RF power supply configured to apply an RF power to the worktable. The apparatus is preset to turn a nitrogen-containing gas and a silicon-containing gas supplied in the process chamber into plasma by the microwaves, and to deposit a silicon nitride film on a surface of the target substrate by use of the plasma, while applying the RF power to the worktable.Type: GrantFiled: May 30, 2007Date of Patent: February 14, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
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Publication number: 20110189862Abstract: Provided is a process of forming a silicon oxynitride film having concentration of hydrogen atoms below or equal to 9.9×1020 atoms/cm3 as measured by using secondary ion mass spectrometry (SIMS), using a plasma CVD device, which generates plasma by introducing microwaves into a process chamber by using a planar antenna having a plurality of apertures, by setting a pressure inside the process chamber within a range from 0.1 Pa to 6.7 Pa, and performing plasma CVD by using process gases including SiCl4 gas, nitrogen gas, and oxygen gas.Type: ApplicationFiled: September 29, 2009Publication date: August 4, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Tatsuo Nishita, Junya Miyahara, Masayuki Kohno
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Publication number: 20110086517Abstract: Disclosed is a plasma CVD device. In the plasma CVD device, in producing a silicon nitride film while controlling the size of a band gap by CVD, microwaves are introduced into a treatment vessel by a flat antenna having a plurality of holes. The plasma CVD is carried out under a given treatment pressure selected from a pressure range of not less than 0.1 Pa and not more than 1333 Pa at a flow ratio between a silicon-containing compound gas and a nitrogen gas (silicon-containing compound gas flow rate/nitrogen gas flow rate) selected from a range of not less than 0.005 and not more than 0.2, whereby the Si/N ratio in the film is controlled to form a silicon nitride film having a band gap size of not less than 2.5 eV and not more than 7 eV.Type: ApplicationFiled: March 30, 2009Publication date: April 14, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Toshio Nakanishi, Masayuki Kohno, Tatsuo Nishita, Junya Miyahara
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Patent number: 7915177Abstract: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration in the gate insulation film formed by the plasma nitridation is 5 to 20% in atomic percentage. Even without subsequent annealing, it is possible to effectively prevent a boron penetration phenomenon in the DRAM and to reduce traps in the film causing deterioration in driving capability of the device.Type: GrantFiled: January 27, 2010Date of Patent: March 29, 2011Assignee: Toyko Electron LimitedInventors: Tatsuo Nishita, Shuuichi Ishizuka, Yutaka Fujino, Toshio Nakanishi, Yoshihiro Sato
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Publication number: 20100283097Abstract: The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.Type: ApplicationFiled: June 20, 2008Publication date: November 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Tetsuo Endoh, Masayuki Kohno, Tatsuo Nishita, Minoru Honda, Toshio Nakanishi, Yoshihiro Hirota