Substrate placing table and substrate processing apparatus
A substrate placing table according to an exemplary embodiment includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.
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This application is a Continuation of U.S. patent application Ser. No. 17/534,150 filed Nov. 23, 2021, which is a Continuation of U.S. patent application Ser. No. 16/721,086 filed Dec. 19, 2019, which is based on and claims the benefit of priority from Japanese Patent Application Nos. 2018-244752 and 2019-203311 filed on Dec. 27, 2018 and Nov. 8, 2019, respectively, with the Japan Patent Office, the entire contents of which are incorporated herein by reference.
TECHNICAL FIELDExemplary embodiments of the present disclosure relate to a substrate placing table and a substrate processing apparatus.
BACKGROUNDA substrate (wafer) placed on a placing table can be held by an electrostatic chuck. The electrostatic chuck electrostatically attracts the wafer to the placing table by an electrostatic force. A placing device disclosed in Japanese Unexamined Patent Publication No. 2008-117982 is provided with a placing body and an electrostatic chuck. An object to be treated is placed on the placing body. The electrostatic chuck is provided with an insulating layer and an electrode layer embedded in the insulating layer. In the electrostatic chuck, voltage is applied to the electrode layer, whereby an electrostatic force is generated between the electrode layer and the object to be treated, and thus the object to be treated is electrostatically attracted to the surface of the insulating layer. An electrostatic chuck layer which is an insulating layer on the surface side of the electrode layer is an yttrium oxide sprayed layer having a thickness in a range of 200 to 280 μm and formed by plasma spraying. The surface of the electrostatic chuck layer is formed with a surface roughness depending on the particle size of yttrium oxide which is thermally sprayed.
SUMMARYIn an exemplary embodiment, a substrate placing table is provided. The substrate placing table includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics.
The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, exemplary embodiments, and features described above, further aspects, exemplary embodiments, and features will become apparent by reference to the drawings and the following detailed description.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The exemplary embodiments described in the detailed description, drawing, and claims are not meant to be limiting. Other exemplary embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.
The present disclosure provides a technique for suppressing an electric discharge between a substrate placing table and a substrate.
Hereinafter, various exemplary embodiments will be described. In an exemplary embodiment, a substrate placing table is provided. The substrate placing table includes a base and an electrostatic chuck provided on the base. The electrostatic chuck includes a lamination layer portion, an intermediate layer, and a covering layer. The lamination layer portion is provided on the base. The intermediate layer is provided on the lamination layer portion. The covering layer is provided on the intermediate layer. The lamination layer portion includes a first layer, an electrode layer, and a second layer. The first layer is provided on the base. The electrode layer is provided on the first layer. The second layer is provided on the electrode layer. The intermediate layer is provided between the second layer and the covering layer and is in close contact with the second layer and the covering layer. The second layer is a resin layer. The covering layer is ceramics. Since it is known that the second layer provided on the electrode layer of the electrostatic chuck in this manner has a relatively high insulation resistance as resin, it is possible to sufficiently reduce the thickness of the second layer while maintaining a predetermined insulation resistance. Therefore, the combined electrostatic capacity of the electrostatic chuck can be increased, and thus the potential between the substrate placed on the substrate placing table and the base can be reduced. For this reason, when voltage is applied to the substrate placing table at a relatively low frequency, a voltage phase difference is reduced, whereby the generation of an electric discharge between the substrate placing table and the substrate can be suppressed.
In the exemplary embodiment, the first layer is a resin layer.
In the exemplary embodiment, the base includes a main body part and a side wall part provided on a side surface of the base. The electrostatic chuck is disposed on the main body part and the side wall part. A diameter of each of the first layer and the second layer is larger than a diameter of the main body part. The first layer and the second layer extend on the base to overlap the side wall part.
In the exemplary embodiment, the intermediate layer includes an end portion region that covers a side surface of the lamination layer portion. The end portion region is in contact with the base and has a tapered shape that is tapered in a direction separated from the lamination layer portion.
In the exemplary embodiment, a taper angle of the end portion region is 45° or less.
In the exemplary embodiment, a material of the first layer and a material of the second layer are any one of polyimide resin, silicone resin, epoxy resin, and acrylic resin.
In the exemplary embodiment, the substrate placing table further includes an end portion region. The end portion region covers a side surface of the lamination layer portion. A material of the end portion region is resin or an insulator. The first layer is an insulating layer or a resin layer.
In the exemplary embodiment, a material of the first layer in a case where the first layer is an insulating layer is ceramic. A material of the first layer in a case where the first layer is a resin layer is any one of polyimide resin, silicone resin, epoxy resin, and acrylic resin. A material of the second layer is any one of polyimide resin, silicone resin, epoxy resin, and acrylic resin.
In the exemplary embodiment, the end portion region made of resin has a tapered shape that is tapered in a direction separated from the lamination layer portion.
In the exemplary embodiment, the base has an insulating region on a surface of the base. The insulating region has a portion extending along a side surface of the lamination layer portion. The end portion region made of resin is provided between the side surface of the lamination layer portion and the portion of the insulating region.
In the exemplary embodiment, the base includes a main body part and a side wall part provided on a side surface of the base. The electrostatic chuck is disposed on the main body part and the side wall part. An inner diameter of each of the first layer and the second layer is smaller than an inner diameter of the main body part. The first layer and the second layer extend on the base to overlap the side wall part. A surface of the side wall part has a portion extending along a side surface of the lamination layer portion. The end portion region made of resin is provided between the side surface of the lamination layer portion and the portion of the surface of the side wall part.
In the exemplary embodiment, a diameter of the electrode layer is smaller than a diameter of each of the first layer and the second layer.
In the exemplary embodiment, the intermediate layer covers an entire surface of the lamination layer portion provided on the base.
In the exemplary embodiment, the intermediate layer covers a part of the side wall part.
In the exemplary embodiment, the covering layer includes a foundation layer and a plurality of protrusion portions. The foundation layer is in close contact with the intermediate layer. The plurality of protrusion portions are provided on an upper surface of the foundation layer.
In the exemplary embodiment, a surface roughness of the upper surface of the foundation layer is in a range of 0.05 to 0.5 μm.
In the exemplary embodiment, the intermediate layer includes a base body and a plurality of granules dispersed in the base body. The plurality of granules include exposed portions exposed from the base body, and the exposed portions are in contact with the second layer and the covering layer.
In the exemplary embodiment, a material of the base body contains resin or a silane-based agent, and a material of the granule is ceramic. The silane-based agent is, for example, an inorganic material containing silicon atoms and oxygen atoms.
In an exemplary embodiment, a substrate processing apparatus is provided. The substrate processing apparatus includes any one of the substrate placing tables described above.
The substrate processing apparatus according to the exemplary embodiment includes a radio frequency power source, and the radio frequency power source is connected to the substrate placing table and supplies radio frequency power of 3 MHz or less to the substrate placing table.
Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In each drawing, identical or equivalent parts are denoted by the same reference numerals. First, an embodiment of the configuration of a substrate placing table 2 will be described with reference to
The substrate placing table 2 is provided in a substrate processing apparatus 1. The substrate processing apparatus 1 can be, for example, a parallel plate type plasma processing apparatus, but is not limited thereto. The substrate processing apparatus 1 is sufficiently provided with devices necessary for plasma processing on a substrate (hereinafter, there is a case where it is referred to as a wafer) placed on the substrate placing table 2. However, details of the configuration of the substrate processing apparatus 1 are not shown in
The substrate placing table 2 has a substantially disk shape extending to intersect a central axis AX. The substrate placing table 2 includes an electrostatic chuck 3 and a base 4. The electrostatic chuck 3 is provided on the base 4. The electrostatic chuck 3 includes a lamination layer portion 3a, an intermediate layer 3b, and a covering layer 3c. The lamination layer portion 3a is provided on the base 4. The intermediate layer 3b is provided on the lamination layer portion 3a. The covering layer 3c is provided on the intermediate layer 3b.
The lamination layer portion 3a includes a layer 3a1 (a first layer), an electrode layer 3a2, and a layer 3a3 (a second layer). The layer 3a1 is provided on the base 4. The electrode layer 3a2 is provided on the layer 3a1. The layer 3a3 is provided on the electrode layer 3a2. The layer 3a3 is a resin layer.
Here, as shown in
Description will be made returning to
The intermediate layer 3b is provided between the layer 3a3 and the covering layer 3c (in particular, the foundation layer 3c1). The intermediate layer 3b is in close contact with the layer 3a3 and the foundation layer 3c1. The base body 3b1 and the granules 3b2 are in contact with the foundation layer 3c1 and also are in contact with the layer 3a3.
A thickness TH1 corresponds to the sum of the thickness of the lamination layer portion 3a and the thickness of the intermediate layer 3b. A thickness TH2 corresponds to the thickness of the lamination layer portion 3a. A thickness TH3 corresponds to the thickness of the covering layer 3c.
The base 4 includes a main body part 4a, a side wall part 4b1, and a side wall part 4b2. The side wall part 4b1 and the side wall part 4b2 are provided on side surfaces SF1 of the main body part 4a. The electrostatic chuck 3 is disposed on the main body part 4a, the side wall part 4b1, and the side wall part 4b2.
The side wall part 4b1 corresponds to the outer wall of the base 4. The side wall part 4b2 corresponds to a sleeve that defines a hole GT penetrating the electrostatic chuck 3 and the base 4 in the base 4. The hole GT can be a hole through which a gas flows, or a hole provided in order to move a pin up and down when placing a wafer W on the substrate placing table 2.
Further, as shown in
The configuration of an end portion of the substrate placing table 2 will be described with reference to
In the end portion of the substrate placing table 2, the intermediate layer 3b includes an end portion region 3bb. The end portion region 3bb covers the side surface SF2 of the lamination layer portion 3a. The end portion region 3bb is in contact with the base 4, and more specifically is in contact with the side wall part 4b1 and the side wall part 4b2.
The end portion region 3bb has a tapered shape that is tapered in a direction separated from the lamination layer portion 3a. In other words, the end portion region 3bb has a thickness that decreases in the direction separated from the lamination layer portion 3a. The thickness of the end portion region 3bb decreases substantially linearly in the direction separated from the lamination layer portion 3a and converges to a thickness TH4.
More specifically, the thickness of the end portion region 3bb converges to the thickness TH4 at a location separated from the lamination layer portion 3a approximately by a length LT3. The length LT3 corresponds to the width of a joined portion between the end portion region 3bb and each of the side wall part 4b1 and the side wall part 4b2.
The tapered shape of the end portion region 3bb is not limited to the shape that is tapered substantially linearly, as shown in
The diameter of the electrode layer 3a2 is smaller than the diameter of each of the layer 3a1 and the layer 3a3. A length LT1 corresponds to ½ of the difference between the diameter of each of the layer 3a1 and the layers 3a3 and the diameter of the electrode layer 3a2.
The diameter of each of the layer 3a1 and the layer 3a3 is larger than the diameter of the main body part 4a. A length LT2 corresponds to ½ of the difference between the diameter of each of the layer 3a1 and the layer 3a3 and the diameter of the main body part 4a. In this manner, the layer 3a1 and the layer 3a3 extend on the base 4 to overlap the side wall part 4b1 and the side wall part 4b2. The intermediate layer 3b covers a part of the side wall part 4b1 and a part of the side wall part 4b2.
According to the substrate placing table 2 having the configuration described above, since the layers 3a1 and 3a3 sandwiching the electrode layer 3a2 of the electrostatic chuck 3 have high insulation resistance, it is possible to sufficiently reduce the thicknesses of the layers 3a1 and 3a3 while maintaining predetermined insulation resistance. Therefore, the combined electrostatic capacity of the electrostatic chuck 3 can be increased, and thus the potential between the substrate placed on the substrate placing table 2 and the base 4 can be reduced. For this reason, when voltage is applied to the substrate placing table 2 at a relatively low frequency, for example, a frequency of 3 MHz or less, a voltage phase difference is reduced, whereby generation of an electric discharge between the substrate placing table and the substrate can be suppressed.
The electrostatic capacity (combined electrostatic capacity) of the electrostatic chuck 3 is made to be in a range of about 10 to 21 pF/cm2. In a case where the electrostatic capacity is smaller than 10 pF/cm2, if a radio frequency power of 3 MHz or less is applied to the substrate placing table, an electric discharge between the substrate placing table and the substrate is easily generated. Further, the upper limit value of the electrostatic capacity that is currently possible is 21 pF/cm2.
The thickness of the electrode layer 3a2 is about 5 μm. The thickness of the layer 3a1 is in a range of about 25 to 50 μm. The relative dielectric constant of the layer 3a1 is about 3.2. The thickness of the layer 3a3 is in a range of about 25 to 50 μm. The relative dielectric constant of the layer 3a3 is about 3.2.
The thickness of an adhesion layer 3a4 is in a range of about 10 to 20 μm. The relative dielectric constant of the adhesion layer 3a4 is about 3.0. The thickness of an adhesion layer 3a5 is in a range of about 10 to 20 μm. The relative dielectric constant of the adhesion layer 3a5 is about 3.0.
The thickness of the intermediate layer 3b is in a range of about 20 to 100 μm. The relative dielectric constant of the intermediate layer 3b is about 2.7. The thickness (the thickness TH3 shown in
The thickness of the foundation layer 3c1 is about 50 μm. The relative dielectric constant of the foundation layer 3c1 is about 7.1. The thickness of the protrusion portion 3c2 is about 15 μm. The relative dielectric constant of the protrusion portion 3c2 is about 7.1.
The surface roughness (arithmetic mean roughness: Ra) of the upper surface 31 of the foundation layer 3c1 is in a range of 0.05 to 0.5 ium. The surface roughness (arithmetic mean roughness: Ra) of an end surface 32 of the protrusion portion 3c2 is in a range of 0.05 to 0.5 μm.
The plurality of protrusion portions 3c2 are provided such that, for example, about 20% of the substrate is in contact therewith.
The length LT1 shown in
A taper angle θ of the end portion region 3bb shown in
The layer 3a1 shown in each of
The material of the base body 3b1 of the intermediate layer 3b contains resin or a silane-based agent. The material of the granule 3b2 is ceramic.
An example of a method of forming the covering layer 3c will be described with reference to
For the execution of the method shown in
Subsequently, ceramic spraying is performed on the intermediate layer 3b of the product PD1, so that a product PD2 is formed. In the ceramic spraying, for example, powder of a thermal spray material having a particle diameter of 15 μm or less is sprayed from a tip portion of a nozzle to a plasma generating portion having the axis common with the nozzle together with a plasma generating gas. Subsequently, plasma is generated from the plasma generation gas with an electric power of 50 kW or less in the plasma generation portion, and the sprayed powder of the thermal spray material is liquefied by the plasma and sprayed so as to cover the surface of the intermediate layer 3b. Since the particle diameter of the powder of the thermal spray material is small and the amount of electric power for melting the powder of the thermal spray material can be reduced, a covering layer 3d can be formed without burnout of the intermediate layer 3b during thermal spraying. In the product PD2, the covering layer 3d is formed on the intermediate layer 3b by ceramic spraying. The covering layer 3c shown in
In the product PD2, the surface of the covering layer 3d is further polished. Due to this polishing, the surface roughness of the surface of the covering layer 3d becomes approximately the same as the surface roughness of the upper surface 31 of the foundation layer 3c1 shown in
Subsequently, a product PD3 is formed by disposing, for example, a resin mask MK1 having a plurality of opening portions on the covering layer 3d of the product PD2. The opening portion of the mask MK1 corresponds to a location where the protrusion portion 3c2 is provided in the covering layer 3c shown in
Subsequently, ceramic spraying is further performed on the product PD3 from above the mask MK1 and the covering layer 3d, so that a product PD4 is formed. The material of ceramics which is used for the formation of the product PD4 is the same as the material of ceramics used for the formation of the covering layer 3d. In the product PD4, the plurality of opening portions of the mask MK1 are filled with ceramics and a mask MK2 made of ceramic is also formed on the mask MK1. In the product PD4, the locations where the plurality of opening portions of the mask MK1 are filled with ceramic correspond to the protrusion portions 3c2 shown in
Subsequently, the mask MK1 and the mask MK2 are removed from the product PD4, so that a product PD5 is formed. In the product PD5, concavities and convexities (the protrusion portion corresponds to the protrusion portion 3c2 shown in
Subsequently, the end surfaces of the protrusion portions of the covering layer 3d of the product PD5 are polished, so that the covering layer 3c is formed from the covering layer 3d, and the substrate placing table 2 is formed. Due to this polishing, the surface roughness of the end surface of the protrusion portion of the covering layer 3d of the product PD5 becomes approximately the same as the surface roughness of the end surface 32 of the protrusion portion 3c2 shown in
The foundation layer 3c1 and the protrusion portions 3c2 are formed as described above, whereby not only the surface roughness of the end surface 32 of the protrusion portion 3c2 but also the surface roughness of the upper surface 31 of the foundation layer 3c1 is reduced. For this reason, for example, when plasma cleaning is performed without placing a substrate, the surface is not easily crushed by the plasma, and therefore, particles which are generated from the foundation layer are sufficiently reduced. The protrusion portion 3c2 is not limited to the formation method using a mask, and for example, the protrusion portion 3c2 may be formed without using a mask after the surface of the covering layer 3d of the product PD2 is polished.
An example of the substrate processing apparatus according to an exemplary embodiment will be described with reference to
A semiconductor wafer (hereinafter referred to as a “wafer W”) which is an example of the substrate is placed on the substrate placing table 2. The substrate placing table 2 also functions as a lower electrode.
A direct-current power source 30 is electrically connected to the electrode layer 3a2 through the contact pin 4d (refer to
A focus ring 11 having an annular shape is placed on the outer periphery side of the electrostatic chuck 3 so as to surround an outer edge portion of the wafer W. The material of the focus ring 11 can be, for example, silicon. The focus ring 11 functions to improve the plasma processing efficiency by converging the plasma toward the surface of the wafer W in the processing container PC.
A refrigerant flow path 12a is formed in the interior of the base 4. A cooling medium (hereinafter also referred to as a “refrigerant”) such as cooling water or brine, for example, output from a chiller 36 flows and circulates through a refrigerant inlet pipe 12b, the refrigerant flow path 12a, and a refrigerant outlet pipe 12c. The substrate placing table 2 made of metal is heat-removed and cooled by the refrigerant circulating in this way.
A heat transfer gas supply source 37 supplies heat transfer gas such as He gas between the front surface of the electrostatic chuck 3 and the back surface of the wafer W through a heat transfer gas supply line 16. With such a configuration, the temperature of the electrostatic chuck 3 is controlled by the refrigerant circulating through the refrigerant flow path 12a and the heat transfer gas which is supplied to the back surface of the wafer W. In this way, the wafer W is controlled to a predetermined temperature.
A first radio frequency power source 33 that supplies radio frequency power HF for plasma generation having a first frequency is connected to the substrate placing table 2 through a first matching device 33a. Further, a second radio frequency power source 34 that supplies radio frequency power LF for bias voltage generation having a second frequency is connected to the substrate placing table 2 through a second matching device 34a. The first frequency is, for example, a radio frequency of 40 MHz, and the first radio frequency power source 33 can supply the radio frequency power HF having the first frequency to the substrate placing table 2. The second frequency is a radio frequency of 3 MHz or less. In the present embodiment, the radio frequency power HF is applied to the substrate placing table 2. However, the radio frequency power HF may be applied to a gas shower head 20.
The first matching device 33a functions such that the internal impedance of the first radio frequency power source 33 and load impedance apparently coincide with each other when plasma is generated in the processing container PC. The second matching device 34a functions such that the internal impedance of the second radio frequency power source 34 and load impedance apparently coincide with each other when plasma is generated in the processing container PC.
The gas shower head 20 is mounted so as to close an opening of a ceiling portion of the processing container PC through a shield ring 21 that covers an outer edge portion of the gas shower head 20. A variable direct-current power source 26 is connected to the gas shower head 20, and a negative direct-current voltage (DC) is output from the variable direct-current power source 26. The gas shower head 20 may be made of silicon. The gas shower head 20 also functions as a counter electrode (an upper electrode) facing the substrate placing table 2 (the lower electrode).
A gas introduction port 22 for introducing gas is formed in the gas shower head 20. A gas diffusion chamber 24a on the center side and a gas diffusion chamber 24b on the edge side, which are branched from the gas introduction port 22, are provided in the interior of the gas shower head 20. The gas output from a gas supply source 23 is supplied to the gas diffusion chamber 24a and the gas diffusion chamber 24b through the gas introduction port 22, and is diffused in the gas diffusion chamber 24a and the gas diffusion chamber 24b and then introduced toward the substrate placing table 2 through a plurality of gas supply holes 25.
An exhaust port 18 is formed in the bottom surface of the processing container PC, and the inside of the processing container PC is exhausted by an exhaust device 38 connected to the exhaust port 18. In this way, the inside of the processing container PC is maintained at a predetermined degree of vacuum. A gate valve 17 is provided on the side wall of the processing container PC. The gate valve 17 is opened and closed when the wafer W is loaded into the processing container PC or unloaded from the processing container PC.
The substrate processing apparatus 1 is provided with a control device 100 that controls the operation of the entire apparatus. The control device 100 includes a CPU 105 (Central Processing Unit), a ROM 110 (Read Only Memory), and a RAM 115 (Random Access Memory). The CPU 105 executes desired plasma processing such as etching according to a recipe stored in a storage area such as the RAM 115. A process time, pressure (gas exhaust), radio frequency power and voltage, various gas flow rates, a temperature in the processing container PC (a temperature of the upper electrode, a side wall temperature of the processing container PC, a temperature of the wafer W, a temperature of the electrostatic chuck 3, or the like), a temperature of the refrigerant from the chiller 36, and the like are set in the recipe.
When plasma processing such as etching or film formation is executed, the opening and closing of the gate valve 17 is controlled, and the wafer W is loaded into the processing container PC and placed on the substrate placing table 2. If a positive or negative direct-current voltage is applied from the direct-current power source 30 to the electrode layer 3a2, the wafer W is electrostatically attracted to and held on the electrostatic chuck 3.
At the time of the process, a desired gas is supplied from the gas supply source 23 into the processing container PC, and the radio frequency power HF is applied from the first radio frequency power source 33 to the substrate placing table 2. The radio frequency power LF may be applied from the second radio frequency power source 34 to the substrate placing table 2. A negative direct-current voltage may be applied from the variable direct-current power source 26 to the gas shower head 20. In this way, the gas is separated above the wafer W, so that plasma is generated, and the wafer W is subjected to plasma processing by the action of the plasma.
After the plasma processing, a direct-current voltage having a polarity opposite to that at the time of the electrostatic attraction is applied from the direct-current power source 30 to the electrode layer 3a2, and thus the electric charges on the wafer W are discharged. After the discharge of the electric charges, the wafer W is peeled off from the electrostatic chuck 3 and unloaded to the outside of the processing container PC through the gate valve 17.
MODIFICATION EXAMPLESEach of
The modification example shown in
In the configuration shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The configuration shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The modification example shown in
The configuration shown in each of
The modification example shown in
The modification example shown in
In the substrate placing table 2 having the configuration shown in each of
According to an exemplary embodiment, a technique for suppressing an electric discharge between the substrate placing table and the substrate can be provided.
Although various exemplary embodiments have been described above, various modified aspect may be configured without being limited to the above-described exemplary embodiments.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.
Claims
1. A substrate support comprising:
- a base; and
- an electrostatic chuck disposed on the base,
- the electrostatic chuck including: a stack disposed on the base, the stack having a side face, the stack including a first insulating layer, a second insulating layer, and an electrode layer disposed between the first insulating layer and the second insulating layer, the electrode layer being covered by one or both of the first insulating layer and the second insulating layer; at least one resin or insulating region covering the side face of the stack and having a curved face; a first cover layer covering the stack and the at least one resin or insulating region; and a second cover layer covering the first cover layer, the second cover layer comprising ceramic material.
2. The substrate support according to claim 1, wherein
- the at least one resin or insulating region includes a resin region and an insulating region,
- the insulating region has the curved face,
- the resin region is disposed between the stack and the insulating region so as to cover the side face of the stack.
3. The substrate support according to claim 2, wherein the curved face is a curved upper face covered by the first cover layer.
4. The substrate support according to claim 1, wherein
- the at least one resin or insulating region includes an insulating region disposed so as to cover the side face of the stack,
- the insulating region has the curved face.
5. The substrate support according to claim 4, wherein the curved face is a curved upper face covered by the first cover layer.
6. The substrate support according to claim 1, wherein the stack has a first adhesion layer disposed between the first insulating layer and the base.
7. The substrate support according to claim 6, wherein the stack has a second adhesion layer disposed between the second insulating layer and the first cover layer.
8. The substrate support according to claim 1, wherein the stack has an adhesion layer disposed between the second insulating layer and the first cover layer.
9. The substrate support according to claim 1, wherein the first insulating layer comprises a ceramic material, or a resin material selected from the group consisting of polyimide, silicone, epoxy and acrylic resins.
10. The substrate support according to claim 9, wherein the second insulating layer comprises a resin material selected from the group consisting of polyimide, silicone, epoxy and acrylic resins.
11. The substrate support according to claim 1, wherein
- the first cover layer comprises a base material and a particulate material dispersed in the base material, and
- at least part of the particulate material is in contact with the second insulating layer and an upper face of the stack.
12. The substrate support according to claim 11, wherein the base material comprises a silicone resin and the particulate material comprises a ceramic material.
13. A plasma processing apparatus comprising:
- a plasma processing chamber;
- a substrate support disposed in the plasma processing chamber, the substrate support comprising: a base; and an electrostatic chuck disposed on the base, the electrostatic chuck including: a stack disposed on the base, the stack having a side face, the stack including a first insulating layer, a second insulating layer, and an electrode layer disposed between the first insulating layer and the second insulating layer, the electrode layer being covered by one or both of the first insulating layer and the second insulating layer; at least one resin or insulating region covering the side face of the stack and having a curved face; a first cover layer covering the stack and the at least one resin or insulating region; and a second cover layer covering the first cover layer, the second cover layer comprising a ceramic material; and
- a RF power source electrically connected to the substrate support.
14. The plasma processing apparatus according to claim 13, wherein the RF power source is configured to generate a RF power having a frequency of 3 MHz or less.
15. The plasma processing apparatus according to claim 14, wherein the RF power source is electrically connected to the base.
16. A substrate support comprising:
- a base; and
- an electrostatic chuck disposed on the base,
- the electrostatic chuck including: a stack disposed on the base, the stack having a side face, the stack including a first insulating layer, a second insulating layer, and an electrode layer disposed between the first insulating layer and the second insulating layer, the electrode layer being covered by one or both of the first insulating layer and the second insulating layer; a resin region covering the side face of the stack and having a rectangular sectional shape; a first cover layer covering the stack and at least one resin or insulating region; and a second cover layer covering the first cover layer, the second cover layer comprising ceramic material.
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Type: Grant
Filed: Oct 17, 2022
Date of Patent: Jun 13, 2023
Patent Publication Number: 20230065448
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Satoshi Taga (Miyagi), Naoyuki Satoh (Miyagi), Tatsuo Nishita (Miyagi)
Primary Examiner: Kevin J Comber
Application Number: 18/047,248
International Classification: H01L 21/683 (20060101); C23C 4/134 (20160101); H01J 37/32 (20060101);