Patents by Inventor Tatsuo Satoh

Tatsuo Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100186766
    Abstract: A cosmetic applicator having bristles which are prevented from becoming rough and spreading. The cosmetic applicator has a shaft section and bristles. The shaft section has at least one recess formed in the outer circumferential surface of a head of a cylindrical shaft body along the longitudinal direction of the shaft section. The bristles are arranged in at least one row along the longitudinal direction and project from interior of the recess beyond the outer circumferential surface of the head of the shaft body.
    Type: Application
    Filed: July 11, 2008
    Publication date: July 29, 2010
    Applicant: SHISEIDO COMPANY, LTD.
    Inventors: Akihito Torii, Motoki Takata, Tatsuo Satoh
  • Patent number: 6006298
    Abstract: In an electronic apparatus having a plurality of printed boards or modules, an on-line module replacement system for allowing the desired of the boards to be inserted or removed while maintaining connecting lines alive allows a plug-in package to be mounted to a backboard without affecting the power supply voltage of other packages. This can be done without resorting to an inductance or similar impedance part heretofore included in a plug-in package.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 21, 1999
    Assignee: NEC Corporation
    Inventor: Tatsuo Satoh
  • Patent number: 4972412
    Abstract: A circuit arrangement for checking excessive time delay in the propagation of signals between two circuit blocks is provided in which two successive square wave clock signals are generated, each having a cycle period equal to the maximum permissible time delay, and a test signal is propagated between the circuit blocks initiated together with the first clock signal. The times of receipt by the second circuit block of the test signal and each clock signal are stored, and means are provided for producing a disparity signal whenever there is a disparity between the two stored signals. A third clock signal is generated which lags the second clock signal and this is compared with the disparity signal to produce an excess delay indicating signal whenever they simultaneously occur.
    Type: Grant
    Filed: December 12, 1988
    Date of Patent: November 20, 1990
    Assignee: NEC Corporation
    Inventor: Tatsuo Satoh
  • Patent number: 4754371
    Abstract: A large scale integrated circuit package is described wherein insulating layers of an organic material are provided between wiring layers to reduce the characteristic impedance of signal wiring. To avoid deformation of the organic insulating layers and subsequent damage to wiring layers, leads for connecting the circuits of an integrated circuit chip to electrode pads are mechanically connected to the electrode pads on an upper layer of organic insulating material by a gold-tin eutectic alloy.
    Type: Grant
    Filed: April 18, 1985
    Date of Patent: June 28, 1988
    Assignee: NEC Corporation
    Inventors: Mitsuru Nitta, Tatsuo Satoh, Tatsuo Inoue