Abstract: A sorting processor has a polygonal priority order generating circuit. The polygonal priority order generating circuit includes a memory for storing information of centers of plural polygons; a position setting section for transforming a coordinate of each of the polygonal centers from an object coordinate to an absolute coordinate; and a visual field transforming circuit for transforming the transformed coordinate as a position set object obtained by the position setting section with respect to a visual field. The sorting processor further has a sorting circuit for sorting transformed results about the visual field on the basis of Z-axis information. There is no frame delay due to a need to wait until the polygonal information is completely sorted. Further, it is not necessary to use a RAM for storing information geometrically transformed before a sorter.

Abstract: An image processing apparatus which can be operated using a small memory capacity and at a high speed. A screen memory for storing X and Y coordinate data for edge points of polygons and a sort memory for storing polygon numbers are provided. A polygon side computing unit computes data for sides of each of the polygons corresponding to each of the polygon numbers. A side pair computing unit computes side pair data in accordance with the data of sides of polygons, the side pair data comprising data of a pair of sides located on the scan lines of the screen. An inclination computing unit computes an inclination of each side of the side pair. A side pair memory stores inclination data and start and end point data of each side of the side pair, each data being stored in a position having a predetermined address. A frame memory stores data for the address of the side pair memory. An interpolation computing unit computes right and left intersection data on each of the scan lines.

Abstract: A polygon extracting unit divides a screen image into n-level hierarchy in a scan-line shifting direction. The polygon extracting unit then accesses the sort memory and then reads data, from the screen memory, concerning the end points of the polygon corresponding to the value obtained as a result of the sort memory access. Then, the same unit, in the highest-level regions of the hierarchy, extracts the polygon edge-pairs overlapping the highest-level region. Then, the same unit, based on polygon edge-information, calculates the information concerning the corresponding edge pair to appear on the scan line. A polygon-edge-pair memory stores data concerning the starting point and ending point of the polygon on the scan line. A transfer unit determines whether or not the extracted polygon edge-pair overlaps with the relevant region. The same unit then transfers the polygon edge-pair to the lower-level regions if the polygon edge-pair overlaps.

Abstract: A clipping processor has a first polygonal end point memory for storing two end point information of X and Y constituting a polygon and respective end point information of mapping information. The clipping processor also has a screen side generating circuit for judging whether a polygonal side crosses each of screen end points and is located inside or outside a screen based on the two end point information from the first polygonal end point memory. The clipping processor further has an intersecting point arithmetic circuit for calculating an intersecting point on the polygonal side at each of the screen end points and respective end point addresses of the mapping information at the intersecting point on the basis of data from the screen side generating circuit.

Abstract: An orthogonal transformation processor has a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation and inputting an output of the memory device thereto; and an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with a switching operation of writing and reading operations of the memory device. Instead of this address generator, the orthogonal transformation processor may have an address generator for designating an address of the memory device and replacing row and column addresses with each other i n accordance with calculating operations of the first and second one-dimensional orthogonal transformation calculators.

Abstract: A circuit for detecting digital data has a data-changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1; an asynchronous detecting circuit for judging whether or not the changing point is caused at a timing synchronized with the timing of the internal clock signal; an asynchronous counter for counting the number of asynchronizations; a synchronous signal generating counter for generating a synchronous signal by the internal clock signal; and a reset control circuit for controlling the timing of a reset operation of the synchronous signal generating counter in accordance with outputs of the data-changing point detecting circuit and the asynchronous counter. Another digital data detecting circuit and a method for detecting digital data are also shown.

Abstract: An image processor has an end point memory for storing two end point information of X and Y constituting a polygon and respective end point information of internal pattern information; an outline processor for performing outline processings of address information of an outline of the polygon and the internal pattern information corresponding to the polygon on the basis of the two end point information and the respective end point information of the internal pattern information from the end point memory; an internal figure-drawing processor for calculating an address between two opposite polygonal sides calculated by the outline processor on the basis of the outline address information, the internal figure-drawing processor calculating an address of the internal pattern information corresponding to the polygonal outline; and a display for displaying image information of a figure.

Abstract: An image data processing apparatus includes a plurality of registers each of which outputs an output signal in accordance with a corresponding signal of a plurality of input coincidence signals derived from the input image data, the output signal indicating whether or not a corresponding register has a maximum count value, and each input coincidence signal indicating whether or not a corresponding pixel among neighborhood pixels of a target pixel of the input image data coincides with a corresponding dot among predetermined reference dots at given locations relative to the location of the target pixel in the input image data, and a state checking part for outputting a state signal indicating whether or not the output signal level of a first register having the maximum count value currently changes from the previous level by detecting the current output signal level of the first register in accordance with the input coincidence signals and in accordance with the output signals of the registers.

Abstract: An orthogonal transformation processor has a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation and inputting an output of the memory device thereto; and an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with a switching operation of writing and reading operations of the memory device. Instead of this address generator, the orthogonal transformation processor may have an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with calculating operations of the first and second one-dimensional orthogonal transformation calculators.

Abstract: An orthogonal transformation processor has a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation and inputting an output of the memory device thereto; and an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with a switching operation of writing and reading operations of the memory device. Instead of this address generator, the orthogonal transformation processor may have an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with calculating operations of the first and second one-dimensional orthogonal transformation calculators.

Abstract: An orthogonal transformation arithmetic unit performs a discrete cosine transformation with respect to a digital signal and compresses discrete cosine transformed data by quantizing and Huffman-coding processings thereof. The arithmetic unit Huffman-decodes the compressed data and demodulates the Huffman-decoded data to a digital signal by performing inverse quantization and an inverse discrete cosine transformation with respect to the Huffman-decoded data. The arithmetic unit has a memory section for storing one line block of image data of brightness and color signals converted to digital signals; and a section for processing the discrete cosine transformation and having a preprocessing circuit for performing adding and subtracting operations with respect to the image data read out of the memory section such that some values of discrete cosine transformation coefficients used in the discrete cosine transformation are partially set to zero. The other orthogonal arithmetic units are also shown.

Abstract: A blood component separation apparatus is disclosed which comprises at least three plate-like members arranged in a stacked fashion, a blood circulation circuit composed of at least two layers which are arranged between the associated plate-like members, a filter for blood component separation which is incorporated into a blood passage, a plurality of connection ports provided in the plate-like members to allow them to communicate with the blood circulation circuit, communication tubes mounted in the blood circulation circuit to place part of the connection ports in communication with an associated connection port, the communication tube being adapted to control a fluid communication in the blood circulation circuit and an external function section connected to corresponding connection ports.

Abstract: The single-needle type plasma separation apparatus of the present invention comprises a blood collection needle; a blood collection container; a first blood transportation tube connecting the blood collection needle to the blood collection container; a blood separator; a second blood transportation tube connecting the blood collection container to a blood inlet of the blood separator; a third blood transportation tube connecting a blood outlet of the blood separator to the first blood transportation tube; a plasma collection container; a plasma transportation tube connecting a plasma outlet of the plasma separator to the plasma collection container; and a blood collection container receptacle including a receiving portion for the blood collection container and capable of pressurizing and depressurizing the interior of the receiving portion.

Abstract: A digital filter processor includes an input part for distributing an input digital data train including a plurality of digital data to a plurality of systems. Each of the systems is provided with a corresopnding one of the distributed data trains at the same time. Each of the systems includes an operation part for multiplying each digital data included in the corresponding one of the distributed data trains by a corresponding multiplication factor at the same time to thereby generate multiplied data and for generating a sum signal indicative of a sum total of the multiplied data related to the corresponding one of the distributed data trains, each of the systems outputting the sum signal at the same time. The operation part also includes a selection part for selecting one of the sum signals supplied from the operation parts provided for the plurality of systems and for outputting an output digital signal.