Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.

Abstract: A magnetic head incorporates: a medium facing surface; a coil; a pole layer; first and second shields disposed to sandwich the pole layer therebetween; a first gap layer disposed between the first shield and the pole layer; a second gap layer disposed between the second shield and the pole layer; and a substrate. The first shield is located closer to the substrate than the second shield. The magnetic head further incorporates an antireflection film disposed between the first shield and the first gap layer or between the first gap layer and the pole layer. The pole layer is formed by frame plating.

Abstract: Provided is a method of manufacturing a perpendicular magnetic recording head which can enhance accuracy and simplify the manufacturing process. The method includes: forming a photoresist pattern having an opening part; forming a non-magnetic layer so as to narrow the opening part by a dry film forming method such as ALD method; stacking a seed layer and a plating layer so as to bury the opening part provided with the non-magnetic layer; and forming a main magnetic pole layer by polishing the non-magnetic layer, the seed layer, and the plating layer by CMP method until the photoresist pattern is exposed. The final opening width is unsusceptible to variations, thus reducing the number of the steps of forming the main magnetic layer.

Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.

Abstract: A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.

Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.

Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.

Abstract: A magnetic head incorporates: a medium facing surface; a coil; a pole layer; first and second shields disposed to sandwich the pole layer therebetween; a first gap layer disposed between the first shield and the pole layer; a second gap layer disposed between the second shield and the pole layer; and a substrate. The first shield is located closer to the substrate than the second shield. The first shield has a first layer and a second layer disposed between the first layer and the first gap layer.

Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.

Abstract: A magnetic head includes: a coil; a pole layer; a shield having an end face located in a medium facing surface forward of an end face of the pole layer along a direction of travel of a recording medium; a gap layer between the shield and the pole layer; and a substrate on which the foregoing elements are stacked. The top surface of the pole layer includes: first and second portions with a difference in height therebetween; and a third portion connecting the first and second portions to each other. The first portion has an edge located in the medium facing surface, and the second portion is located farther from the medium facing surface and from the substrate than the first portion. The magnetic head further includes a nonmagnetic layer disposed between the second portion and the gap layer. The nonmagnetic layer has a surface touching the second portion, the surface having an edge located at the boundary between the second and third portions.

Abstract: Provided is a method of manufacturing a perpendicular magnetic recording head which can enhance accuracy and simplify the manufacturing process. The method includes: forming a photoresist pattern having an opening part (the inclination of an inner wall); forming a non-magnetic layer (the inclination of another inner wall) so as to narrow the opening part by a dry film forming method such as ALD method; stacking a seed layer and a plating layer so as to bury the opening part provided with the non-magnetic layer; and forming a main magnetic pole layer (a front end portion having a bevel angle) by polishing the non-magnetic layer, the seed layer, and the plating layer by CMP method until the photoresist pattern is exposed. The final opening width (the forming width of the front end portion) is unsusceptible to variations, thus reducing the number of the steps of forming the main magnetic layer.

Abstract: Provided is a method of manufacturing a perpendicular magnetic recording head which can enhance accuracy and simplify the manufacturing process. The method includes: forming a photoresist pattern having an opening part (the inclination of an inner wall); forming a non-magnetic layer (the inclination of another inner wall) so as to narrow the opening part by a dry film forming method such as ALD method; stacking a seed layer and a plating layer so as to bury the opening part provided with the non-magnetic layer; and forming a main magnetic pole layer (a front end portion having a bevel angle) by polishing the non-magnetic layer, the seed layer, and the plating layer by CMP method until the photoresist pattern is exposed. The final opening width (the forming width of the front end portion) is unsusceptible to variations, thus reducing the number of the steps of forming the main magnetic layer.

Abstract: A thin film magnetic head integrated structure is provided. A plurality of thin film magnetic head bars include a plurality of thin film magnetic head precursors, a plurality of RLG sensors for read head core, and a plurality of RLG sensors for write head core, the read head core including a magnetoresistive element that performs a read process and the write head core including a magnetic pole layer that performs a write process.

Abstract: An image data processing system has a learning storage apparatus that stores projection matrixes obtained by canonical correlation analysis so as to derive, based on at least one of an image feature and a word feature, a latent variable as an abstract concept used for associating an image with a word corresponding thereto and that further stores information required for obtaining the latent variable acquired by use of the projection matrixes, a probability of occurrence of an arbitrary image feature from a certain latent variable and a probability of occurrence of an arbitrary word feature from a certain latent variable. In this way, a probability of the image feature and word feature being simultaneously outputted can be easily and quickly determined, thereby executing a high-speed annotation or retrieval with high precision.

Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.