Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A thin-film magnetic head includes a first magnetic layer, a flat, spiral-shaped coil, a toroidal-shaped insulating layer covering the coil, and a second magnetic layer touching the insulating layer and disposed to sandwich part of the coil between itself and the first magnetic layer. The second magnetic layer has a recessed portion that enters a space inside the insulating layer. In the recessed portion, the bottom surface of the second magnetic layer includes a first flat portion a part of which touches the top surface of the first magnetic layer, while the top surface of the second magnetic layer includes a second flat portion located in the space and substantially parallel to the first flat portion. In a cross section that divides each of the first and second magnetic layers into two equal portions, the second flat portion is 0.

Abstract: A seat belt retractor may include: a motor that generates a driving force for retracting and unreeling a seat belt by rotating a shaft, a gear case has an interior portion that houses a gear that converts a rotary force of the shaft into a driving force, a harness connected to a side of the motor including the shaft that is disposed opposite the gear case, a motor case having an opening disposed in only one end thereof, and a motor cap disposed on a side of the motor including the shaft opposing the gear case. The motor cap may include a passage portion through which the harness passes to an exterior thereof. The opening in the motor case may be sealed by attaching the motor case to the motor cap and the gear case in a sandwiched manner.

Abstract: A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.

Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.

Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.

Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.

Abstract: A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of first-type layer portions each including a first-type semiconductor chip; and a second-type layer portion including a second-type semiconductor chip. The first-type semiconductor chip includes a plurality of memory cells. The second-type semiconductor chip includes a control circuit that controls writing and reading on and from the memory cells included in the plurality of first-type layer portions. Each layer portion includes an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each of the electrodes has an end face that is located at the side surface of the main body and connected to the wiring.

Abstract: A magnetic head includes: a coil; a pole layer; a shield having an end face located in a medium facing surface forward of an end face of the pole layer along a direction of travel of a recording medium; a gap layer between the shield and the pole layer; and a substrate on which the foregoing elements are stacked. The top surface of the pole layer includes: first and second portions with a difference in height therebetween; and a third portion connecting the first and second portions to each other. The first portion has an edge located in the medium facing surface, and the second portion is located farther from the medium facing surface and from the substrate than the first portion. The magnetic head further includes a nonmagnetic layer disposed between the second portion and the gap layer. The nonmagnetic layer has a surface touching the second portion, the surface having an edge located at the boundary between the second and third portions.

Abstract: A thin-film magnetic head includes a first magnetic layer, a flat, spiral-shaped coil, a toroidal-shaped insulating layer covering the coil, and a second magnetic layer touching the insulating layer and disposed to sandwich part of the coil between itself and the first magnetic layer. The second magnetic layer has a recessed portion that enters a space inside the insulating layer. In the recessed portion, the bottom surface of the second magnetic layer includes a first flat portion a part of which touches the top surface of the first magnetic layer, while the top surface of the second magnetic layer includes a second flat portion located in the space and substantially parallel to the first flat portion. In a cross section that divides each of the first and second magnetic layers into two equal portions, the second flat portion is 0.

Abstract: A thin-film magnetic head with which an error rate is decreased due to a reduction of a jitter without significant decrease in write field, is provided. The head comprises at least one inductive write head element comprising: a main magnetic pole layer having an inner saturation magnetic flux density varying from both side end surfaces in a track-width direction and a leading end surface, toward a center portion in the track-width direction of a trailing end surface; an auxiliary magnetic pole layer; and at least one coil layer, a curvature width WC of a contour line of a write field adjacent to a trailing edge on an ABS side of the main magnetic pole layer satisfying the following expression: ?0.15*WT?WC<12 where WT is a track width and a unit of WC and WT is nanometer.

Abstract: A magnetic head incorporates: a medium facing surface; a coil; a pole layer; first and second shields disposed to sandwich the pole layer therebetween; a first gap layer disposed between the first shield and the pole layer; a second gap layer disposed between the second shield and the pole layer; and a substrate. The first shield is located closer to the substrate than the second shield. The first shield has a first layer and a second layer disposed between the first layer and the first gap layer.

Abstract: A magnetic head incorporates: a medium facing surface; a coil; a pole layer; first and second shields disposed to sandwich the pole layer therebetween; a first gap layer disposed between the first shield and the pole layer; a second gap layer disposed between the second shield and the pole layer; and a substrate. The first shield is located closer to the substrate than the second shield. The magnetic head further incorporates an antireflection film disposed between the first shield and the first gap layer or between the first gap layer and the pole layer. The pole layer is formed by frame plating.

Abstract: A invention provides a method of manufacturing a thin film magnetic head is provided, capable of forming a magnetic pole layer as easily as possible. By etching a lower insulating layer and the upper insulating layer by RIE using a fluorine-based gas (CF4 or CHF3) or chlorine-based gas (Cl2 or BCl3), a magnetic pole formation space R1 is formed so as to have a uniform width in an upper insulating layer by and a magnetic pole formation space R2 is formed in the lower insulating layer so as to have a width gradually narrowed from width W1 to width W4 with distance from the magnetic pole formation space R1. After that, a plating film is grown in the magnetic pole formation spaces R1 and R2, thereby forming a main magnetic pole layer.

Abstract: Provided is a method of manufacturing a perpendicular magnetic recording head which can enhance accuracy and simplify the manufacturing process. The method includes: forming a photoresist pattern having an opening part (the inclination of an inner wall); forming a non-magnetic layer (the inclination of another inner wall) so as to narrow the opening part by a dry film forming method such as ALD method; stacking a seed layer and a plating layer so as to bury the opening part provided with the non-magnetic layer; and forming a main magnetic pole layer (a front end portion having a bevel angle) by polishing the non-magnetic layer, the seed layer, and the plating layer by CMP method until the photoresist pattern is exposed. The final opening width (the forming width of the front end portion) is unsusceptible to variations, thus reducing the number of the steps of forming the main magnetic layer.