Patents by Inventor Tatsuya Hashinaga

Tatsuya Hashinaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096736
    Abstract: A high-frequency amplifier includes a driver amplifier, a Doherty amplifier including carrier and peak amplifiers which amplify the driver amplifier output, a second substrate laminated on a first substrate, and a base member mounted with the first and second substrates. The driver amplifier is mounted on the second substrate, and the carrier and peak amplifiers are mounted on the first substrate. A front surface of the driver amplifier opposes the first substrate, and a back surface of the driver amplifier is separated from the first substrate. Back surfaces of the carrier and peak amplifiers contact the base member, and the back surface of the driver amplifier connects to an interconnect layer disposed on the second substrate and connected to one end of a via penetrating the second and first substrates, and the other end of the via connects to the base member.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Publication number: 20250080053
    Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Patent number: 12199572
    Abstract: A high-frequency amplifier includes a driver amplifier, a Doherty amplifier including carrier and peak which amplify the driver amplifier output, a second substrate laminated on a first substrate, and a base member mounted with the first and second substrates. The driver amplifier is mounted on the second substrate, and the carrier and peak amplifiers are mounted on the first substrate. A front surface of the driver amplifier opposes the first substrate, and a back surface of the driver amplifier is separated from the first substrate. Back surfaces of the carrier and peak amplifiers contact the base member, and the back surface of the driver amplifier connects to an interconnect layer disposed on the second substrate and connected to one end of a via penetrating the second and first substrates, and the other end of the via connects to the base member.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: January 14, 2025
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tatsuya Hashinaga, Yutaka Moriyama
  • Patent number: 12176860
    Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.
    Type: Grant
    Filed: January 18, 2024
    Date of Patent: December 24, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tatsuya Hashinaga, Yutaka Moriyama
  • Publication number: 20240395754
    Abstract: A semiconductor device includes a substrate having a first main surface and a second main surface opposite the first main surface. The semiconductor device includes a gate pad and a drain pad provided on the first main surface, and includes a source pad provided on the second main surface. The semiconductor device includes a first bump provided on the gate pad, the first bump including a plurality of first stud bumps stacked over one another. The semiconductor device includes a second bump provided on the drain pad, the second bump including a plurality of second stud bumps stacked over one another. The semiconductor device includes an insulating resin layer provided around the first bump and the second bump.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 28, 2024
    Inventors: Yutaka MORIYAMA, Tatsuya HASHINAGA
  • Patent number: 12051998
    Abstract: An amplifier circuit includes a first amplifier that amplifies a high frequency signal, and a load circuit that changes a load impedance of the first amplifier without being controlled by an external circuit so that a saturation power at a first temperature is higher than a saturation power at a second temperature lower than the first temperature, and an efficiency at the first temperature is lower than an efficiency at the second temperature.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: July 30, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tatsuya Hashinaga
  • Publication number: 20240154575
    Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Patent number: 11916519
    Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: February 27, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tatsuya Hashinaga, Yutaka Moriyama
  • Publication number: 20230290750
    Abstract: A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.
    Type: Application
    Filed: January 11, 2023
    Publication date: September 14, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Tatsuya HASHINAGA
  • Publication number: 20230290752
    Abstract: A semiconductor device includes a metal plate having a base portion and a terminal portion separated from the base portion, a resin layer provided between the base portion and the terminal portion and so as to surround the metal plate in a planar direction, and at which an upper and a lower surface of each of the base portion and the terminal portion are exposed, a semiconductor chip mounted on the base portion, a first electrically insulating layer provided on the metal plate and the resin layer so as to cover the semiconductor chip, and one or more wires provided on the first electrically insulating layer and including at least one wire configured to electrically connect the semiconductor chip and the terminal portion to each other.
    Type: Application
    Filed: February 7, 2023
    Publication date: September 14, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaka MORIYAMA, Tatsuya HASHINAGA
  • Publication number: 20230291358
    Abstract: A high-frequency device includes a metal base, a dielectric substrate mounted on the metal base, an insulator layer provided on the metal base, covering the dielectric substrate, and having a dielectric constant smaller than that of the dielectric substrate, and a first line that overlaps the dielectric substrate as seen from a thickness direction of the insulator layer and is provided on an upper surface of the insulator layer to form a first microstrip line.
    Type: Application
    Filed: January 25, 2023
    Publication date: September 14, 2023
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Tatsuya HASHINAGA
  • Publication number: 20220416727
    Abstract: An amplifier circuit includes a first amplifier that amplifies a high frequency signal, and a load circuit that changes a load impedance of the first amplifier without being controlled by an external circuit so that a saturation power at a first temperature is higher than a saturation power at a second temperature lower than the first temperature, and an efficiency at the first temperature is lower than an efficiency at the second temperature.
    Type: Application
    Filed: April 22, 2022
    Publication date: December 29, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tatsuya HASHINAGA
  • Publication number: 20220376658
    Abstract: A high frequency amplifier includes an asymmetric Doherty amplifier configured to amplify a high frequency signal having a wavelength A, the high frequency signal being input, and the asymmetric Doherty amplifier including a carrier amplifier and a peak amplifier, the peak amplifier being configured to start an amplifying operation when an output of the carrier amplifier reaches a saturation region and having a saturation output different from a saturation output of the carrier amplifier, a driver amplifier configured to drive the asymmetric Doherty amplifier, a branch circuit configured to branch the high frequency signal amplified by the driver amplifier into an input path on a peak amplifier side and an input path on a carrier amplifier side, a phase adjustment circuit configured to delay either a phase of a signal input to the peak amplifier or a phase of a signal input to the carrier amplifier, the phase adjustment circuit being provided on either the input path on the peak amplifier side or the input pa
    Type: Application
    Filed: January 5, 2021
    Publication date: November 24, 2022
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Publication number: 20220329209
    Abstract: A high-frequency amplifier includes a driver amplifier configured to amplify an input high-frequency signal, a Doherty amplifier, including a carrier amplifier and a peak amplifier, and configured to further amplify a signal output from the driver amplifier, a first multilayer substrate, a second multilayer substrate laminated to overlap the first multilayer substrate, and a base member mounted with the first multilayer substrate and the second multilayer substrate, wherein the driver amplifier is mounted on the second multilayer substrate, the carrier amplifier and the peak amplifier are mounted on the first multilayer substrate, the driver amplifier, the carrier amplifier, and the peak amplifier have a front surface forming a predetermined circuit, and a back surface located on an opposite side from the front surface, respectively, the front surface of the driver amplifier opposes the first multilayer substrate, and the back surface of the driver amplifier is separated from the first multilayer substrate, t
    Type: Application
    Filed: December 25, 2020
    Publication date: October 13, 2022
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Patent number: 11444575
    Abstract: Included are: a first power source 3 configured to output a voltage required for a first gate bias voltage for turning a power amplifier 2 to an ON state; a second power source 4 configured to output a voltage required for a second gate bias voltage for turning the power amplifier 2 to an OFF state; a changeover switch 5 connected between the first power source 3 and the power amplifier 2 and configured to supply either the first gate bias voltage or the second gate bias voltage to the power amplifier 2 by switching a state between the first power source 3 and the power amplifier 2 to either an open state or a short-circuit state on the basis of a control signal related to on-off control of the power amplifier 2; and a resistance value varying unit 15 connected between the second power source 4 and the power amplifier 2 and configured such that a resistance value thereof is variable.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: September 13, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki Tango, Tatsuya Hashinaga, Harutoshi Tsuji
  • Patent number: 11152900
    Abstract: A multistage amplifier includes: N amplifiers (N?2), a (k+1)th amplifier cascaded to a kth amplifier (1?k?N?1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a jth amplifier (1?j?N?1), and the output providing a compensation signal to an input of a (j+1)th amplifier or an output of the (j+1)th amplifier. The extraction circuit includes a filter circuit connected to the output of the jth amplifier that extracts a distortion frequency component of n times a differential frequency f2?f1 (n?1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 19, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tatsuya Hashinaga
  • Publication number: 20210320625
    Abstract: A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×???/4 to (2n+1)×?+?/4, where n is an integer greater than or equal to zero.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 14, 2021
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Publication number: 20210265237
    Abstract: A semiconductor device includes an insulating substrate having a first surface, a semiconductor chip that is embedded in the insulating substrate and has a second surface exposed in the first surface, and a heat dissipation layer that is in contact with the first surface and the second surface and has a plated layer.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 26, 2021
    Inventors: Tatsuya HASHINAGA, Yutaka MORIYAMA
  • Publication number: 20210135629
    Abstract: Included are: a first power source 3 configured to output a voltage required for a first gate bias voltage for turning a power amplifier 2 to an ON state; a second power source 4 configured to output a voltage required for a second gate bias voltage for turning the power amplifier 2 to an OFF state; a changeover switch 5 connected between the first power source 3 and the power amplifier 2 and configured to supply either the first gate bias voltage or the second gate bias voltage to the power amplifier 2 by switching a state between the first power source 3 and the power amplifier 2 to either an open state or a short-circuit state on the basis of a control signal related to on-off control of the power amplifier 2; and a resistance value varying unit 15 connected between the second power source 4 and the power amplifier 2 and configured such that a resistance value thereof is variable.
    Type: Application
    Filed: January 13, 2021
    Publication date: May 6, 2021
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki TANGO, Tatsuya HASHINAGA, Harutoshi TSUJI
  • Patent number: 10924064
    Abstract: Included are: a first power source 3 configured to output a voltage required for a first gate bias voltage for turning a power amplifier 2 to an ON state; a second power source 4 configured to output a voltage required for a second gate bias voltage for turning the power amplifier 2 to an OFF state; a changeover switch 5 connected between the first power source 3 and the power amplifier 2 and configured to supply either the first gate bias voltage or the second gate bias voltage to the power amplifier 2 by switching a state between the first power source 3 and the power amplifier 2 to either an open state or a short-circuit state on the basis of a control signal related to on-off control of the power amplifier 2; and a resistance value varying unit 15 connected between the second power source 4 and the power amplifier 2 and configured such that a resistance value thereof is variable.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 16, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki Tango, Tatsuya Hashinaga, Harutoshi Tsuji