Patents by Inventor Tatsuya Kanda
Tatsuya Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9305736Abstract: Provided is a phosphor for a dispersion-type EL that may be manufactured in a simple process and may provide stable, high brightness and light emission efficiency. The phosphor for a dispersion-type EL according to the present invention includes a mixture of an electron-accepting phosphor particle (4A) and an electron-donating phosphor particle (4B). The electron-accepting phosphor particle (4A) includes a base particle and an acceptor element added thereto, and the electron-donating phosphor particle (4B) includes a base particle and a donor element added thereto. For example, the base particle is a ZnS particle, the acceptor element is Cu, and the donor element is Cl or Al.Type: GrantFiled: July 11, 2012Date of Patent: April 5, 2016Assignee: TAZMO CO., LTD.Inventors: Koichi Wani, Tatsuya Kanda, Emi Hashimoto, Kazushi Kawakami, Sadahiro Yagishita, Fumitaka Iwakura, Taku Nishikawa
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Publication number: 20140138590Abstract: Provided is a phosphor for a dispersion-type EL that may be manufactured in a simple process and may provide stable, high brightness and light emission efficiency. The phosphor for a dispersion-type EL according to the present invention includes a mixture of an electron-accepting phosphor particle (4A) and an electron-donating phosphor particle (4B). The electron-accepting phosphor particle (4A) includes a base particle and an acceptor element added thereto, and the electron-donating phosphor particle (4B) includes a base particle and a donor element added thereto. For example, the base particle is a ZnS particle, the acceptor element is Cu, and the donor element is Cl or Al.Type: ApplicationFiled: July 11, 2012Publication date: May 22, 2014Applicant: TAZMO CO., LTD.Inventors: Koichi Wani, Tatsuya Kanda, Emi Hashimoto, Kazushi Kawakami, Sadahiro Yagishita, Fumitaka Iwakura, Taku Nishikawa
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Patent number: 8077537Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: GrantFiled: November 4, 2009Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 8015389Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: December 19, 2007Date of Patent: September 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 8004921Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: GrantFiled: November 4, 2009Date of Patent: August 23, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7814294Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: January 26, 2007Date of Patent: October 12, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7774577Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: December 19, 2007Date of Patent: August 10, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20100172200Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: July 8, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro KAWAKUBO, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20100146201Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: June 10, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7729200Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: December 18, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7684258Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.Type: GrantFiled: February 13, 2007Date of Patent: March 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tatsuya Kanda, Kotoku Sato
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Patent number: 7668040Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: February 16, 2007Date of Patent: February 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20090027988Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: December 19, 2007Publication date: January 29, 2009Applicant: Toyoda Gosei Co., Ltd.Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7471585Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: GrantFiled: August 24, 2006Date of Patent: December 30, 2008Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
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Publication number: 20080211689Abstract: An illegal-parking-management portable terminal includes a storage unit, an extracting unit, and a selecting unit. The storage unit stores therein facility information on a facility relevant to illegal parking and an illegal-parking application rule that defines illegal-parking condition for each penalty article. The extracting unit extracts, from the facility information, information on a facility within a predetermined range from a position specified as a vehicle parking position on a map displayed on a display unit. The selecting unit compares the extracted information with the illegal-parking application rule, and selects a penalty article to be applied to illegal parking of a vehicle.Type: ApplicationFiled: May 1, 2008Publication date: September 4, 2008Applicants: FUJITSU LIMITED, FFC LIMITEDInventors: Kunikazu Takahashi, Tatsuya Kanda, Masahiro Oota, Levan Higashigawa
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Publication number: 20080189467Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: ApplicationFiled: December 18, 2007Publication date: August 7, 2008Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080181027Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: December 19, 2007Publication date: July 31, 2008Inventors: Takahiro Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151678Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: ApplicationFiled: February 16, 2007Publication date: June 26, 2008Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151670Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: February 23, 2007Publication date: June 26, 2008Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151677Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: January 26, 2007Publication date: June 26, 2008Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato