Abstract: A first ECU and a plurality of second ECUs are connected to a communication bus. The first ECU repeatedly transmits a beacon signal through the communication bus. Each of the first ECU and the plurality of second ECUs transmits data according to an order set in advance when the beacon signal is transmitted. The first ECU or the second ECU transmits dummy data whose transmission destination is different from the remaining ECUs when there is no transmission data to be transmitted to one of the remaining ECUs other than itself.

Abstract: In order to assist participants in thinking of an idea by acquiring audio data, it is provided a workshop assistance system, which includes a computer having an arithmetic apparatus configured to execute predetermined processing, a storage device coupled to the arithmetic apparatus, and a communication interface coupled to the arithmetic apparatus, the computer being configured to access solved problem case data including information of solved cases that correspond to problem data, the workshop assistance system comprising: a problem processing module configured to search, by the arithmetic apparatus, solved cases based on problem data that is generated from a discussion among participants; and an idea generation module configured to present, by the arithmetic apparatus, idea data including the generated problem data and information of the solved case found in the search to the participants.

Abstract: A control device to be mounted on a vehicle includes a memory configured to store information related to priority levels of a plurality of applications that implements driving assistance functions and a processor. The processor is configured to receive, from the applications, application requests and identifiers that identify the respective applications. The processor is configured to arbitrate a plurality of the application requests based on the information and the identifiers. The processor is configured to output a request to an actuator based on a result of arbitration of the application requests.

Abstract: A semiconductor device includes: a substrate; a buffer layer; an intermediate layer; an electron transport layer; an electron supply layer; a source electrode and a drain electrode; and a gate electrode. The intermediate layer includes a stack resulting from stacking a first intermediate layer and a second intermediate layer. The second intermediate layer is provided above the first intermediate layer. A first position that is 100 nm above a lower surface of the intermediate layer is in the first intermediate layer. A second position that is 100 nm below an upper surface of the intermediate layer is in the second intermediate layer. A value obtained by dividing a density of edge screw mixed dislocations with a Burgers vector of <11-23>/3 at the second position by a density of edge screw mixed dislocations with the Burgers vector of <11-23>/3 at the first position is at most 0.66.

Abstract: Provided is a phosphor for a dispersion-type EL that may be manufactured in a simple process and may provide stable, high brightness and light emission efficiency. The phosphor for a dispersion-type EL according to the present invention includes a mixture of an electron-accepting phosphor particle (4A) and an electron-donating phosphor particle (4B). The electron-accepting phosphor particle (4A) includes a base particle and an acceptor element added thereto, and the electron-donating phosphor particle (4B) includes a base particle and a donor element added thereto. For example, the base particle is a ZnS particle, the acceptor element is Cu, and the donor element is Cl or Al.

Abstract: Provided is a phosphor for a dispersion-type EL that may be manufactured in a simple process and may provide stable, high brightness and light emission efficiency. The phosphor for a dispersion-type EL according to the present invention includes a mixture of an electron-accepting phosphor particle (4A) and an electron-donating phosphor particle (4B). The electron-accepting phosphor particle (4A) includes a base particle and an acceptor element added thereto, and the electron-donating phosphor particle (4B) includes a base particle and a donor element added thereto. For example, the base particle is a ZnS particle, the acceptor element is Cu, and the donor element is Cl or Al.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

Abstract: An illegal-parking-management portable terminal includes a storage unit, an extracting unit, and a selecting unit. The storage unit stores therein facility information on a facility relevant to illegal parking and an illegal-parking application rule that defines illegal-parking condition for each penalty article. The extracting unit extracts, from the facility information, information on a facility within a predetermined range from a position specified as a vehicle parking position on a map displayed on a display unit. The selecting unit compares the extracted information with the illegal-parking application rule, and selects a penalty article to be applied to illegal parking of a vehicle.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.