Patents by Inventor Tatsuya Kobayashi
Tatsuya Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190067250Abstract: A semiconductor device includes a base including interconnects, a first semiconductor chip including a first semiconductor element portion, and a second semiconductor chip including a second semiconductor element portion. The second semiconductor chip is electrically connected to the first semiconductor chip via at least one of the interconnects. The second semiconductor chip includes a first region, a first portion, and a second portion. The first region includes the second semiconductor element portion. The first portion is continuous with the first region. The second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction. The first direction is from the base toward the first region. The second portion, the first portion, and at least a portion of the first semiconductor chip each is positioned between the base and the first region.Type: ApplicationFiled: June 4, 2018Publication date: February 28, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Akira Tojo, Tatsuya Kobayashi, Masayuki Uchida, Takashi Ito, Kazuo Shimokawa
-
Patent number: 10134665Abstract: A BGA 9 includes a wiring substrate 2, a semiconductor chip 1 fixed on the wiring substrate 2, a sealing body 4 that seals the semiconductor chip 1, and a plurality of solder balls 5 provided on a lower surface of the wiring substrate 2. A degree of flatness of an upper surface 2ia of a first wiring layer 2i of the wiring substrate 2 of the BGA 9 is lower than a degree of flatness of a lower surface 2ib, and a first pattern 2jc provided in a second wiring layer 2j is arranged at a position overlapping a first pattern 2ic provided in the first wiring layer 2i. Also, an area of the first pattern 2ic provided in the first wiring layer 2i is larger than an area of a plurality of (for example, two) second patterns 2jd provided in the second wiring layer 2j in a plan view, and a first opening portion 2jm through which a part of a second insulating layer 2h is exposed is formed in the first pattern 2jc provided in the second wiring layer 2j.Type: GrantFiled: July 3, 2015Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Tatsuya Kobayashi, Soshi Kuroda
-
Patent number: 10128940Abstract: An optical transmission method wavelength-multiplexing and transmitting multiple channels including data. The data are composed of data areas independent between the channels and data areas non-independent between the channels. Data patterns of the data areas non-independent between the channels are variable. The data patterns of the data areas non-independent between the channels are set so that in time periods of the non-independent data areas on an optical transmission section, a time period during which polarization states of the multiple channels are correlated in the optical transmission section has a length such that an error rate is less than or equal to a threshold value, the error rate being determined from a temporal distribution of bit errors obtained from a result of error decision after demodulation in an optical receiver.Type: GrantFiled: April 16, 2015Date of Patent: November 13, 2018Assignee: Mitsubishi Electric CorporationInventors: Hiroki Goto, Tsuyoshi Yoshida, Kiyoshi Onohara, Takashi Sugihara, Kazuo Kubo, Tatsuya Kobayashi, Keisuke Matsuda, Masashi Binkai
-
Patent number: 10128153Abstract: a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves. The device and the method can provide higher productivity.Type: GrantFiled: June 14, 2016Date of Patent: November 13, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Tajima, Kazuo Shimokawa, Tatsuya Kobayashi
-
Publication number: 20180315691Abstract: An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.Type: ApplicationFiled: April 17, 2018Publication date: November 1, 2018Inventor: Tatsuya KOBAYASHI
-
Publication number: 20180309535Abstract: A dummy-light generating device includes a continuous wave (CW) light source that outputs CW light, a modulated-light generating unit that generates, using the CW light, first intensity-modulated light subjected to intensity modulation and second intensity-modulated light delayed by a half time of a modulation cycle of the first intensity-modulated light with respect to the first intensity-modulated light and having a polarization state e different from a polarization state e of the first intensity-modulated light, and a polarization combiner that performs polarization combination of the first intensity-modulated light and second intensity-modulated light and outputs light after the polarization combination as dummy light.Type: ApplicationFiled: April 27, 2015Publication date: October 25, 2018Applicant: Mitsubishi Electric CorporationInventors: Seiki NAKAMURA, Tsuyoshi YOSHIDA, Keisuke MATSUDA, Tatsuya KOBAYASHI
-
Publication number: 20180286819Abstract: A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface. The device layer includes a second semiconductor element electrically connected to the first semiconductor element, and is provided on the first surface of the substrate. The film includes a first film including a first region, a second region, and a third region. The substrate is positioned between the first region and the device layer in a first direction. The substrate is positioned between the second region and the third region in a second direction crossing the first direction. The first film fills the unevenness of the second surface and the side surface.Type: ApplicationFiled: March 6, 2018Publication date: October 4, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Akira Tojo, Tatsuya Kobayashi, Kazuo Shimokawa
-
Patent number: 10022055Abstract: A blood pressure information measurement device cuff includes a wide blood pressure value measurement air bladder wrapped around a fitting area when in a fitted state, and a narrow pulse wave measurement air bladder disposed so as to be closer to the fitting area than the blood pressure value measurement air bladder when in the fitted state, and covered by the blood pressure value measurement air bladder when wrapped around the fitting area. The pulse wave measurement air bladder includes an anchored portion anchored to the blood pressure value measurement air bladder so as to be immobile relative to the blood pressure value measurement air bladder and a mobile portion that is not anchored to the blood pressure value measurement air bladder so as to be mobile relative to the blood pressure value measurement air bladder along a wrapping direction in which the cuff is wrapped around the measurement area.Type: GrantFiled: October 1, 2012Date of Patent: July 17, 2018Assignee: OMRON HEALTHCARE Co., Ltd.Inventors: Tatsuya Kobayashi, Kenji Fujii, Yukiya Sawanoi, Naoto Akiyama
-
Patent number: 9983540Abstract: An image forming apparatus of the present disclosure is provided with a main body-side substrate, a cover member, a metallic main body frame, and a metallic thumbscrew. The main body-side substrate is provided in a main body of the image forming apparatus, and an electrical component is mountable thereto. The cover member covers an outer side of the main body-side substrate. The cover member is secured to the main body frame. The thumbscrew is used to secure the cover member to the main body frame. The cover member is demounted from the main body frame by unscrewing the thumbscrew, and thus mounting of the electrical component with respect to the main body-side substrate is enabled.Type: GrantFiled: July 27, 2017Date of Patent: May 29, 2018Assignee: KYOCERA Document Solutions Inc.Inventor: Tatsuya Kobayashi
-
Patent number: 9972555Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.Type: GrantFiled: July 27, 2017Date of Patent: May 15, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Soshi Kuroda, Tatsuya Kobayashi, Takanori Aoki
-
Patent number: 9961969Abstract: A belt includes a belt main body extending in a long, narrow band. A frame-shaped body is attached to a first belt portion corresponding to a side on an end in a lengthwise direction of the belt main body. Multiple through-holes are formed in alignment in the lengthwise direction in a second belt portion corresponding to a side opposite to the first belt portion in the lengthwise direction of the belt main body. A locking member is included for attachment to a through-hole of the second belt portion so as to protrude from a front surface of the second belt portion. When the belt main body is mounted on the target object, the second belt portion is passed through the frame-shaped body, and the side of the frame-shaped body locks the locking member so as to prevent the second belt portion from coming out of the frame-shaped body.Type: GrantFiled: November 30, 2016Date of Patent: May 8, 2018Assignee: OMRON HEALTHCARE Co., Ltd.Inventors: Yasuhiro Kawabata, Tatsuya Kobayashi, Reiji Fujita, Hiroshi Nakamori
-
Publication number: 20180090429Abstract: A BGA 9 includes a wiring substrate 2, a semiconductor chip 1 fixed on the wiring substrate 2, a sealing body 4 that seals the semiconductor chip 1, and a plurality of solder balls 5 provided on a lower surface of the wiring substrate 2. A degree of flatness of an upper surface 2ia of a first wiring layer 2i of the wiring substrate 2 of the BGA 9 is lower than a degree of flatness of a lower surface 2ib, and a first pattern 2jc provided in a second wiring layer 2j is arranged at a position overlapping a first pattern 2ic provided in the first wiring layer 2i. Also, an area of the first pattern 2ic provided in the first wiring layer 2i is larger than an area of a plurality of (for example, two) second patterns 2jd provided in the second wiring layer 2j in a plan view, and a first opening portion 2jm through which a part of a second insulating layer 2h is exposed is formed in the first pattern 2jc provided in the second wiring layer 2j.Type: ApplicationFiled: July 3, 2015Publication date: March 29, 2018Applicant: Renesas Electronics CorporationInventors: Tatsuya KOBAYASHI, Soshi KURODA
-
Publication number: 20180052418Abstract: An image forming apparatus of the present disclosure is provided with a main body-side substrate, a cover member, a metallic main body frame, and a metallic thumbscrew. The main body-side substrate is provided in a main body of the image forming apparatus, and an electrical component is mountable thereto. The cover member covers an outer side of the main body-side substrate. The cover member is secured to the main body frame. The thumbscrew is used to secure the cover member to the main body frame. The cover member is demounted from the main body frame by unscrewing the thumbscrew, and thus mounting of the electrical component with respect to the main body-side substrate is enabled.Type: ApplicationFiled: July 27, 2017Publication date: February 22, 2018Applicant: KYOCERA Document Solutions Inc.Inventor: Tatsuya KOBAYASHI
-
Publication number: 20180033709Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.Type: ApplicationFiled: July 27, 2017Publication date: February 1, 2018Inventors: Soshi KURODA, Tatsuya KOBAYASHI, Takanori AOKI
-
Publication number: 20170360162Abstract: A belt of the present invention includes a belt main body (10) that extends in the form of a long. narrow band. A frame-shaped body (13) is attached to a first belt portion (11) corresponding to a side on an end in a lengthwise direction (Y) of the belt main body (10). Multiple through-holes (21, 22; 21, 22; . . . ) are formed in alignment in the lengthwise direction (Y) in the second belt portion (12) corresponding to a side opposite to the first belt portion (11) in the lengthwise direction (Y) of the belt main body (10). A locking member (14) is included which is to be attached to a through-hole (21, 22) of the second belt portion (12) so as to protrude from a front surface (12a) of the second belt portion (12).Type: ApplicationFiled: November 30, 2016Publication date: December 21, 2017Applicant: OMRON HEALTHCARE Co., Ltd.Inventors: Yasuhiro Kawabata, Tatsuya Kobayashi, Reiji Fujita, Hiroshi Nakamori
-
Patent number: 9723999Abstract: An electronic blood pressure meter includes a cuff that is to be worn on a measurement area, a piezoelectric pump that adjusts a pressure applied to the cuff, a drive circuit that drives the piezoelectric pump, and a controller that outputs, to the drive circuit, a pulse signal defining a driving timing of the piezoelectric pump. The drive circuit includes a switching circuit for switching a connection relationship between respective voltages applied to both ends of the piezoelectric pump in response to corresponding first and second driving signals, and a signal generation circuit that outputs the first and second driving signals based on the pulse signal outputted from the controller. The signal generation circuit has a signal conditioning circuit that adjusts timings of the first and second driving signals so that the phases of the first and second driving signals do not overlap.Type: GrantFiled: October 5, 2012Date of Patent: August 8, 2017Assignee: OMRON HEALTHCARE Co., Ltd.Inventors: Yuki Yamashita, Tatsuya Kobayashi
-
Publication number: 20170208829Abstract: An object of the present invention is to provide a powdered fat and/or oil composition, a food containing the powdered fat and/or oil composition, and methods for producing these. Specifically, provided are a fat and/or oil composition containing 65 to 99% by mass of a XXX triglyceride and 35 to 1% by mass of X2Y triglycerides, a powdered fat and/or oil composition obtained from the fat and/or oil composition, a food containing the powdered fat and/or oil composition, and methods for producing these.Type: ApplicationFiled: July 22, 2015Publication date: July 27, 2017Applicant: THE NISSHIN OILLIO GROUP, LTD.Inventors: Kiyomi OONISHI, Tomohiro AIBARA, Noriko MURAYAMA, Muneo TSUKIYAMA, Seiya TAKEGUCHI, Hidetaka UEHARA, Tatsuya KOBAYASHI, Hirofumi DENDA
-
Patent number: D780818Type: GrantFiled: April 13, 2016Date of Patent: March 7, 2017Assignee: Nikon CorporationInventor: Tatsuya Kobayashi
-
Patent number: D783072Type: GrantFiled: April 13, 2016Date of Patent: April 4, 2017Assignee: Nikon CorporationInventors: Masaaki Yanagisawa, Tatsuya Kobayashi
-
Patent number: D846618Type: GrantFiled: December 22, 2016Date of Patent: April 23, 2019Assignee: Nikon Vision Co., Ltd.Inventor: Tatsuya Kobayashi