Patents by Inventor Tatsuya Ogi
Tatsuya Ogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10418289Abstract: A method performed by a semiconductor manufacturing apparatus includes calculating, by a processor of the semiconductor manufacturing apparatus, 3 standard deviations of process condition measurements obtained at a predetermined interval from log information of processing of substrates that have been correctly processed, calculating at least one of an upper limit and a lower limit for anomaly detection based on the calculated 3 standard deviations, and detecting an anomaly in the processing of the substrates based on the at least one of the upper limit and the lower limit.Type: GrantFiled: September 1, 2017Date of Patent: September 17, 2019Assignee: Tokyo Electron LimitedInventors: Tatsuya Ogi, Hiroaki Mochizuki
-
Publication number: 20180068906Abstract: A method performed by a semiconductor manufacturing apparatus includes calculating, by a processor of the semiconductor manufacturing apparatus, 3 standard deviations of process condition measurements obtained at a predetermined interval from log information of processing of substrates that have been correctly processed, calculating at least one of an upper limit and a lower limit for anomaly detection based on the calculated 3 standard deviations, and detecting an anomaly in the processing of the substrates based on the at least one of the upper limit and the lower limit.Type: ApplicationFiled: September 1, 2017Publication date: March 8, 2018Inventors: Tatsuya OGI, Hiroaki MOCHIZUKI
-
Patent number: 9299540Abstract: Provided is a parallel flat-panel type plasma processing apparatus which includes a recipe storing unit storing a processing recipe for performing a plasma processing, a compensation setting unit setting an accumulation time of the plasma processing or the number of processed substrates after starting using a new second electrode and the compensation value of the set temperature of the second electrode in an input screen, and a storage unit storing the compensated set value. The plasma processing apparatus is further equipped with a program for controlling a temperature adjusting mechanism based on a set temperature after compensation by adding a set temperature of an upper electrode written in the processing recipe to the compensation value stored within the storage unit. As a result, the non-uniformity in the plasma processing between the substrates caused by the change of processing atmosphere is suppressed.Type: GrantFiled: September 16, 2014Date of Patent: March 29, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Tatsuya Ogi, Wataru Ozawa, Kimihiro Fukasawa, Kazuhiro Kanaya
-
Patent number: 9002494Abstract: There is provided a substrate transfer method capable of preventing fine particles from adhering to a wafer. A substrate processing system 10 includes process modules 12 to 17 each having therein an inner space S1; a transfer module 11, having an inner space S2, connected to the process modules 12 to 17; and opening/closing gate valves 30 each partitioning the inner space S1 and the inner space S2. The transfer module 11 includes in the inner space S2 a transfer arm device 21 for holding a wafer W and for loading/unloading the wafer W into/from the process modules 12 to 17. The transfer arm device 21 holds the wafer W at a retreated position deviated from a facing position facing the gate valve 30 during an opening motion of the gate valve 30.Type: GrantFiled: September 6, 2011Date of Patent: April 7, 2015Assignee: Tokyo Electron LimitedInventors: Eiki Endo, Tatsuya Ogi
-
Publication number: 20150001181Abstract: Provided is a parallel flat-panel type plasma processing apparatus which includes a recipe storing unit storing a processing recipe for performing a plasma processing, a compensation setting unit setting an accumulation time of the plasma processing or the number of processed substrates after starting using a new second electrode and the compensation value of the set temperature of the second electrode in an input screen, and a storage unit storing the compensated set value. The plasma processing apparatus is further equipped with a program for controlling a temperature adjusting mechanism based on a set temperature after compensation by adding a set temperature of an upper electrode written in the processing recipe to the compensation value stored within the storage unit. As a result, the non-uniformity in the plasma processing between the substrates caused by the change of processing atmosphere is suppressed.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Tatsuya OGI, Wataru OZAWA, Kimihiro FUKASAWA, Kazuhiro KANAYA
-
Patent number: 8864934Abstract: Provided is a parallel flat-panel type plasma processing apparatus which includes a recipe storing unit storing a processing recipe for performing a plasma processing, a compensation setting unit setting an accumulation time of the plasma processing or the number of processed substrates after starting using a new second electrode and the compensation value of the set temperature of the second electrode in an input screen, and a storage unit storing the compensated set value. The plasma processing apparatus is further equipped with a program for controlling a temperature adjusting mechanism based on a set temperature after compensation by adding a set temperature of an upper electrode written in the processing recipe to the compensation value stored within the storage unit. As a result, the non-uniformity in the plasma processing between the substrates caused by the change of processing atmosphere is suppressed.Type: GrantFiled: March 29, 2012Date of Patent: October 21, 2014Assignee: Tokyo Electron LimitedInventors: Tatsuya Ogi, Wataru Ozawa, Kimihiro Fukasawa, Kazuhiro Kanaya
-
Patent number: 8663489Abstract: A method for replacing plural substrates to be processed by a substrate processing apparatus which includes a substrate processing chamber, a load lock chamber, and a conveying apparatus including first and second conveying members for conveying the plural substrates into and out from the substrate processing chamber and the load lock chamber. The method includes the steps of a) conveying a first substrate out from the substrate processing chamber with the first conveying member, b) conveying a second substrate into the substrate processing chamber with the second conveying member, c) conveying the second substrate out from the load lock chamber with the second conveying member, and d) conveying the first substrate into the load lock chamber with the first conveying member. The steps c) and d) are performed between step a) and step b).Type: GrantFiled: March 26, 2010Date of Patent: March 4, 2014Assignee: Tokyo Electron LimitedInventors: Shigeru Ishizawa, Hiroshi Koizumi, Tatsuya Ogi
-
Patent number: 8423176Abstract: In a substrate processing apparatus according to the present invention, wafer transfer timing with which wafers are to be transferred to individual processing chambers from a cassette container is determined in correspondence to each processing chamber, based upon the lengths of time required to process a single wafer in the processing chambers. Then, wafers are transferred from the cassette container in conformance to the transfer timing thus determined. By setting the wafer transfer timing with which wafers are transferred from the cassette container in coordination with the lengths of processing time at the individual processing chambers, the operation rates in the processing chambers are improved and ultimately, the throughput of the apparatus is improved.Type: GrantFiled: September 15, 2011Date of Patent: April 16, 2013Assignee: Tokyo Electron LimitedInventor: Tatsuya Ogi
-
Publication number: 20120248067Abstract: Provided is a parallel flat-panel type plasma processing apparatus which includes a recipe storing unit storing a processing recipe for performing a plasma processing, a compensation setting unit setting an accumulation time of the plasma processing or the number of processed substrates after starting using a new second electrode and the compensation value of the set temperature of the second electrode in an input screen, and a storage unit storing the compensated set value. The plasma processing apparatus is further equipped with a program for controlling a temperature adjusting mechanism based on a set temperature after compensation by adding a set temperature of an upper electrode written in the processing recipe to the compensation value stored within the storage unit. As a result, the non-uniformity in the plasma processing between the substrates caused by the change of processing atmosphere is suppressed.Type: ApplicationFiled: March 29, 2012Publication date: October 4, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Tatsuya Ogi, Wataru Ozawa, Kimihiro Fukasawa, Kazuhiro Kanaya
-
Publication number: 20120101758Abstract: A method of analyzing a cause of abnormality of a wafer processed by plasma in at least any one of two or more process modules disposed in a plasma processing system of a cluster type, the method includes recording information about transfer paths of the processing target from when the wafer is transferred from a shipping container and transferred to at least any one of the two or more process modules to when the processing target is returned to the shipping container, in relation with identification information of the wafer for each processing target; testing a state of the wafer after a plasma process has finished; and analyzing a cause of abnormality based on a result of comparison between recorded informations about transfer paths of the processing target determined to be abnormal and the processing target determined to be normal as a result of the testing.Type: ApplicationFiled: October 24, 2011Publication date: April 26, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Tatsuya OGI
-
Patent number: 8140181Abstract: A substrate transfer method for use in a substrate processing apparatus including a first processing unit that performs a first process on a substrate, a second processing unit performing a second process on the substrate, and a substrate transfer mechanism that transfers the substrate between the first and the second processing unit, includes: detecting misalignment of the substrate when the substrate is unloaded from the first processing unit; and correcting the misalignment of the substrate based on a detected result. Further, the substrate transfer method includes loading the misalignment-corrected substrate to a targeted position in the second processing unit.Type: GrantFiled: October 8, 2009Date of Patent: March 20, 2012Assignee: Tokyo Electron LimitedInventor: Tatsuya Ogi
-
Publication number: 20120059502Abstract: There is provided a substrate transfer method capable of preventing fine particles from adhering to a wafer. A substrate processing system 10 includes process modules 12 to 17 each having therein an inner space S1; a transfer module 11, having an inner space S2, connected to the process modules 12 to 17; and opening/closing gate valves 30 each partitioning the inner space S1 and the inner space S2. The transfer module 11 includes in the inner space S2 a transfer arm device 21 for holding a wafer W and for loading/unloading the wafer W into/from the process modules 12 to 17. The transfer arm device 21 holds the wafer W at a retreated position deviated from a facing position facing the gate valve 30 during an opening motion of the gate valve 30.Type: ApplicationFiled: September 6, 2011Publication date: March 8, 2012Applicant: Tokyo Electron LimitedInventors: Eiki Endo, Tatsuya Ogi
-
Publication number: 20120004753Abstract: In a substrate processing apparatus according to the present invention, wafer transfer timing with which wafers are to be transferred to individual processing chambers from a cassette container is determined in correspondence to each processing chamber, based upon the lengths of time required to process a single wafer in the processing chambers. Then, wafers are transferred from the cassette container in conformance to the transfer timing thus determined. By setting the wafer transfer timing with which wafers are transferred from the cassette container in coordination with the lengths of processing time at the individual processing chambers, the operation rates in the processing chambers are improved and ultimately, the throughput of the apparatus is improved.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Tatsuya OGI
-
Patent number: 8078311Abstract: In a substrate processing apparatus according to the present invention, wafer transfer timing with which wafers are to be transferred to individual processing chambers from a cassette container is determined in correspondence to each processing chamber, based upon the lengths of time required to process a single wafer in the processing chambers. Then, wafers are transferred from the cassette container in conformance to the transfer timing thus determined. By setting the wafer transfer timing with which wafers are transferred from the cassette container in coordination with the lengths of processing time at the individual processing chambers, the operation rates in the processing chambers are improved and ultimately, the throughput of the apparatus is improved.Type: GrantFiled: November 30, 2005Date of Patent: December 13, 2011Assignee: Tokyo Electron LimitedInventor: Tatsuya Ogi
-
Publication number: 20100252532Abstract: A method for replacing plural substrates to be processed by a substrate processing apparatus which includes a substrate processing chamber, a load lock chamber, and a conveying apparatus including first and second conveying members for conveying the plural substrates into and out from the substrate processing chamber and the load lock chamber. The method includes the steps of a) conveying a first substrate out from the substrate processing chamber with the first conveying member, b) conveying a second substrate into the substrate processing chamber with the second conveying member, c) conveying the second substrate out from the load lock chamber with the second conveying member, and d) conveying the first substrate into the load lock chamber with the first conveying member. The steps c) and d) are performed between step a) and step b).Type: ApplicationFiled: March 26, 2010Publication date: October 7, 2010Inventors: SHIGERU ISHIZAWA, Hiroshi Koizumi, Tatsuya Ogi
-
Publication number: 20100094452Abstract: A substrate transfer method for use in a substrate processing apparatus including a first processing unit that performs a first process on a substrate, a second processing unit performing a second process on the substrate, and a substrate transfer mechanism that transfers the substrate between the first and the second processing unit, includes: detecting misalignment of the substrate when the substrate is unloaded from the first processing unit; and correcting the misalignment of the substrate based on a detected result. Further, the substrate transfer method includes loading the misalignment-corrected substrate to a targeted position in the second processing unit.Type: ApplicationFiled: October 8, 2009Publication date: April 15, 2010Applicant: TOKYO ELECTRON LIMITEDInventor: Tatsuya OGI
-
Publication number: 20060182533Abstract: In a substrate processing apparatus according to the present invention, wafer transfer timing with which wafers are to be transferred to individual processing chambers from a cassette container is determined in correspondence to each processing chamber, based upon the lengths of time required to process a single wafer in the processing chambers. Then, wafers are transferred from the cassette container in conformance to the transfer timing thus determined. By setting the wafer transfer timing with which wafers are transferred from the cassette container in coordination with the lengths of processing time at the individual processing chambers, the operation rates in the processing chambers are improved and ultimately, the throughput of the apparatus is improved.Type: ApplicationFiled: November 30, 2005Publication date: August 17, 2006Applicant: TOKYO ELECTRON LIMITEDInventor: Tatsuya Ogi
-
Patent number: 6711454Abstract: In a system and method for scheduling the movement of wafers in a wafer-processing tool, the wafer-processing tool can include a load module, a wafer-transfer unit, a process module, and a scheduler. The scheduler can be configured to generate a schedule for the movement of wafers in the wafer-processing tool based on the duration of the operations to be performed by the wafer-transfer unit and the process module in processing the wafers.Type: GrantFiled: February 11, 2003Date of Patent: March 23, 2004Assignee: Tokyo Electron, Ltd.Inventors: Kentaro Joma, Tatsuya Ogi
-
Publication number: 20030120371Abstract: In a system and method for scheduling the movement of wafers in a wafer-processing tool, the wafer-processing tool can include a load module, a wafer-transfer unit, a process module, and a scheduler. The scheduler can be configured to generate a schedule for the movement of wafers in the wafer-processing tool based on the duration of the operations to be performed by the wafer-transfer unit and the process module in processing the wafers.Type: ApplicationFiled: February 11, 2003Publication date: June 26, 2003Inventors: Kentaro Joma, Tatsuya Ogi
-
Patent number: 6535784Abstract: In a system and method for scheduling the movement of wafers in a wafer-processing tool, the wafer-processing tool can include a load module, a wafer-transfer unit, a process module, and a scheduler. The scheduler can be configured to generate a schedule for the movement of wafers in the wafer-processing tool based on the duration of the operations to be performed by the wafer-transfer unit and the process module in processing the wafers.Type: GrantFiled: April 26, 2001Date of Patent: March 18, 2003Assignee: Tokyo Electron, Ltd.Inventors: Kentaro Joma, Tatsuya Ogi