Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. The second and third transistors share a metal oxide. The capacitor is provided between the first and second transistors. An insulator is provided over an electrode functioning as a source or a drain of the first transistor, and the insulator has an opening reaching the electrode. The capacitor is provided in the opening. One electrode of the capacitor includes, in the opening, a region in contact with the other of the source electrode and the drain electrode of the first transistor. The one electrode of the capacitor includes a region in contact with a gate electrode of the second transistor.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A storage device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode and a second electrode. The second capacitor includes the first electrode and a third electrode. One of a source and a drain of the first transistor is electrically connected to the second electrode; one of a source and a drain of the second transistor is electrically connected to the third electrode; and the first electrode includes a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor and is supplied with a fixed potential or a ground potential.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor. The first memory cell and the second memory cell each include a transistor and a capacitor. One of a source and a drain of the transistor is electrically connected to a lower electrode of the capacitor. The first conductor includes a portion in contact with the other of the source and the drain of the transistor included in the first memory cell. A top surface of the first conductor includes a portion in contact with a bottom surface of the second conductor. The second conductor includes a portion in contact with the other of the source and the drain of the transistor included in the second memory cell.

Abstract: An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

Abstract: A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

Abstract: A novel storage device is provided. A storage device in which N memory layers each including a plurality of memory cells provided in a matrix (Nis an integer greater than or equal to 2) are stacked is provided. A write bit line, a read bit line, and a selection line are provided along a stacking direction of the memory layers, and a write word line and a read word line are provided in the direction orthogonal to the stacking direction of the memory layers. The memory cell includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to the write bit line through a first conductor including a region functioning as one of a source electrode and a drain electrode. The first conductor includes a region where at least one of the top surface, a side surface, and the bottom surface of the first conductor is in contact with the write bit line.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided.

Abstract: A semiconductor device with high manufacturing yield is provided. The semiconductor device includes a plurality of subpixels. Each of the subpixels includes a first transistor, a second transistor, a first capacitor to a third capacitor, a first insulating layer, and a wiring. Each of the first capacitor to the third capacitor includes a first conductive layer, a second conductive layer, and a second insulating layer sandwiched between the first conductive layer and the second conductive layer. The first insulating layer is provided over the first transistor and the second transistor. The first conductive layers of the first capacitor to the third capacitor and the wiring are each provided over the first insulating layer. In a top view, the proportion of the total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to the area of the subpixel is greater than or equal to 15 percent.

Abstract: An electronic device including a first conductor, a second conductor, a first insulator, a second insulator, and a connection electrode is provided. The first insulator is provided over the first conductor and has a first opening overlapping with the first conductor. The second conductor is provided over the first insulator and has a second opening overlapping with the first conductor. The second insulator is provided over the second conductor and has a third opening overlapping with the first conductor. The second opening has a portion having a width smaller than a width of the third opening. The connection electrode is positioned inside the first opening, the second opening, and the third opening and is in contact with the top surface of the first conductor. The connection electrode includes a region in contact with part of the top surface and part of the side surface of the second conductor.

Abstract: Provided is a multifunctional display device or a multifunctional electronic device. Provided is a display device or electronic device with high visibility. Provided is a display device or electronic device with low power consumption. The electronic device includes a housing, a display device, a system unit, a camera, a secondary battery, a reflective surface, and a wearing tool. The system unit and the secondary battery are each positioned inside the housing. The system unit includes a charging circuit unit. The charging circuit unit is configured to control charging of the secondary battery. The system unit is configured to perform first processing based on imaging data of the camera. The first processing includes at least one of gesture operation, head tracking, and eye tracking. The system unit is configured to generate image data based on the first processing. The display device is configured to display the image data.

Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. In each of the first to third transistors, the side surfaces of a metal oxide are covered with a source electrode and a drain electrode. The second and third transistors share the metal oxide. The capacitor is provided above the first to third transistors. A conductor including a region functioning as a write bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the first transistor. A conductor including a region functioning as a read bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the third transistor.

Abstract: A semiconductor device that can be scaled down or highly integrated is to be provided. The semiconductor device includes a first conductor, a second conductor, a first insulator, a first transistor over the first insulator, and a second insulator over the first transistor. The first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, a third insulator over the first metal oxide, and a fifth conductor over the third insulator. The top surface of the fifth conductor includes a region in contact with the second insulator. The first conductor includes a portion positioned on an inner side of an opening of the first insulator, a region in contact with the side surface of the third conductor, and a portion positioned on an inner side of an opening of the second insulator.

Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor and a second transistor over an insulating surface; the first transistor and the second transistor share a metal oxide and a first conductor over the metal oxide; the first transistor includes a second conductor and a first insulator over the metal oxide and a third conductor over the first insulator; the second transistor includes a fourth conductor and a second insulator over the metal oxide and a fifth conductor over the second insulator; the first insulator is positioned in a region between the first conductor and the second conductor; the metal oxide and the third conductor overlap with each other with the first insulator therebetween; the second insulator is positioned in a region between the first conductor and the fourth conductor; and the metal oxide and the fifth conductor overlap with each other with the second insulator therebetween.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: A correction method of a display apparatus is provided. A method for evaluating display quality of a display apparatus is provided. The display apparatus includes a display panel, a correction circuit, and a memory. First, first imaging data including all pixels in the display apparatus is acquired in a state where an image with a first grayscale is displayed on the display apparatus. Then, second imaging data including all the pixels in the display apparatus is acquired in a state where an image with a second grayscale is displayed on the display apparatus. Next, correction data is generated based on the first imaging data and the second imaging data. After that, the correction data is output to the memory of the display apparatus. The correction circuit has a function of correcting image data based on the correction data stored in the memory to generate corrected image data and outputting the corrected image data to the display panel.

Abstract: Provided is a display system with high display quality and high resolution. The display system includes a first layer and a display portion. The display portion is positioned in a region overlapping with the first layer. The first layer includes a semiconductor substrate containing silicon as a material, and a plurality of first transistors and a plurality of second transistors whose channel formation regions contain silicon are formed over the semiconductor substrate. The first layer includes a first circuit and a second circuit; the first circuit includes a driver circuit for driving the display portion; and the second circuit includes a memory device, a GPU, and an EL correction circuit. The display portion includes a pixel, and the pixel includes a light-emitting device containing organic EL and is electrically connected to the driver circuit.

Abstract: A semiconductor device having a large storage capacity per unit area is provided.