Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: A display apparatus that can display a high-resolution image can be provided. In the display apparatus, a first layer and a second layer are stacked. In the first layer, an arithmetic circuit and a data driver circuit and are provided, and in the second layer, a display portion is provided. In the arithmetic circuit, a neural network is configured. The display portion has a region overlapping with the data driver circuit. The arithmetic circuit has a function of performing arithmetic processing using the neural network on image data and supplying the arithmetically-processed image data to the data driver circuit.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

Abstract: A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.

Abstract: A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

Abstract: One embodiment of the present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. The imaging device is formed by bonding a plurality of layers or stacks each including a device to each other. A pixel circuit; a memory circuit; and a pixel driver circuit, a driver circuit of the memory circuit, and the like can be provided for a first layer, a second layer, and a third layer, respectively. With such a structure, a small imaging device can be formed. Furthermore, wiring delay or the like can be inhibited by stacking the circuits, so that a high-speed operation can be performed.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.

Abstract: A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

Abstract: A structure that includes a circuit for controlling the safe operation of a secondary battery but can overcome space limitations owing to miniaturization of the housing is provided. A charge control circuit is provided over a flexible substrate and bonded to an external surface of the secondary battery. The charge control circuit is electrically connected to at least one of two terminals of the secondary battery and controls charging. To prevent overcharge, both an output transistor of a charging circuit and a blocking switch are brought into off state substantially concurrently. Blocking two paths which connect to the battery can quickly stop charging when overcharge is detected and reduce damage to the battery owing to the overcharge.

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer. The first element layer includes a first memory cell, a first electrode, a second electrode, and a third electrode. The first memory cell includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The first electrode is electrically connected to the third electrode via the second electrode. The third electrode is provided to be exposed on a surface of the first element layer. The first through electrode is provided to be exposed on a surface of the second substrate and is electrically connected to the first electrode.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

Abstract: To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line.

Abstract: A novel display device is provided. The display device includes a first layer including a driver circuit, a second layer including a plurality of pixel circuits, and a third layer including a plurality of light-emitting elements; the second layer is provided over the first layer; the third layer is provided over the second layer; and a conductive layer is provided between the driver circuit and the plurality of pixel circuits. The driver circuit has a function of controlling operations of the plurality of pixel circuits. One of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements. The pixel circuit has a function of controlling emission luminance of the light-emitting element.

Abstract: A high-resolution or high-definition display device is provided.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a first layer; a second layer over the first layer; and a third layer over the second layer. The first layer includes a functional circuit including a first transistor, the second layer includes a plurality of pixel circuits each including a second transistor, the third layer includes a plurality of light-emitting elements, one of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements, the functional circuit has a function of controlling an operation of the pixel circuit, and the pixel circuit has a function of controlling emission luminance of the light-emitting element.

Abstract: A semiconductor device includes a first transistor one of a source and a drain of which is electrically connected to a first wiring for reading data; a second transistor one of a source and a drain of which is electrically connected to a gate of the first transistor and the other of the source and the drain of which is electrically connected to a second wiring for writing the data; and a third transistor one of a source and a drain of which is electrically connected to the gate of the first transistor and the other of the source and the drain of which is electrically connected to a capacitor for retaining electric charge corresponding to the data, and the third transistor includes a metal oxide in a channel formation region.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.