Patents by Inventor Tatsuya Onuki

Tatsuya Onuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230004704
    Abstract: The circuit layout generation system includes a memory portion, a limitation data arithmetic portion, and a layout data arithmetic portion. The memory portion is configured to store circuit connection data and first limitation data. The circuit connection data is data regarding connection of a transistor and a capacitor included in a pixel circuit. The first limitation data includes data that determines a wiring interval of the transistor and a wiring interval of the capacitor and data that determines placement coordinates of the transistor and the capacitor. The limitation data arithmetic portion is configured to generate second limitation data on the basis of the circuit connection data and the first limitation data and store the second limitation data in the memory portion. The second limitation data is data that determines the placement of the transistor and the capacitor designated by the placement coordinates so that the transistor and the capacitor are positioned close to each other.
    Type: Application
    Filed: June 22, 2022
    Publication date: January 5, 2023
    Inventors: Munehiro KOZUMA, Minato ITO, Yusuke KOUMURA, Tatsuya ONUKI
  • Publication number: 20220392521
    Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuki OKAMOTO, Tatsuya ONUKI
  • Publication number: 20220375956
    Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.
    Type: Application
    Filed: November 13, 2020
    Publication date: November 24, 2022
    Inventors: Hitoshi KUNITAKE, Satoru OHSHITA, Kazuki TSUDA, Tatsuya ONUKI
  • Publication number: 20220367509
    Abstract: A semiconductor device having a large storage capacity per unit area is provided.
    Type: Application
    Filed: June 23, 2020
    Publication date: November 17, 2022
    Inventors: Shunpei YAMAZAKI, Tatsuya ONUKI, Satoru OKAMOTO
  • Publication number: 20220350571
    Abstract: A novel information processing device with least signal transmission delay and low power consumption is provided. A storage device includes a first layer, a second layer, and a third layer. The first layer is provided with a circuit. The second layer is provided with a memory cell portion. The third layer is provided with a first electrode. The circuit has a function of switching and performing reading or writing of first data or second data from or to the memory cell portion. At least part of the second layer is stacked above the first layer. At least part of the third layer is stacked above the second layer. An arithmetic device includes a fourth layer and a fifth layer. The fourth layer is provided with a central processing device. The fifth layer is provided with a second electrode. At least part of the fifth layer is stacked above the fourth layer. The circuit is electrically connected to the central processing device through the first electrode and the second electrode.
    Type: Application
    Filed: November 25, 2020
    Publication date: November 3, 2022
    Inventors: Shunpei YAMAZAKI, Takayuki IKEDA, Tatsuya ONUKI, Hitoshi KUNITAKE
  • Patent number: 11476862
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 18, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Yuto Yakubo, Kiyoshi Kato, Seiya Saito
  • Publication number: 20220328487
    Abstract: A semiconductor device with a novel structure is provided. One embodiment of the present invention is a semiconductor device including a memory module. The memory module includes a first memory cell, a first wiring, and a second wiring and a third wiring that include a metal oxide. The first memory cell includes a read transistor and a rewrite transistor. The first wiring includes a region functioning as a back gate of the read transistor and a region where the second wiring functions as a conductor. The second wiring includes a region functioning as a channel formation region of the read transistor, a region functioning as a back gate of the rewrite transistor, and a region where the third wiring functions as a conductor. The third wiring includes a region functioning as a channel formation region of the rewrite transistor and a region functioning as a conductor.
    Type: Application
    Filed: August 17, 2020
    Publication date: October 13, 2022
    Inventors: Hajime KIMURA, Tatsuya ONUKI, Hitoshi KUNITAKE
  • Publication number: 20220328092
    Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Takahiko ISHIZU, Tatsuya ONUKI
  • Publication number: 20220328486
    Abstract: A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 13, 2022
    Inventors: Tatsuya ONUKI, Takanori MATSUZAKI, Shunpei YAMAZAKI
  • Publication number: 20220320117
    Abstract: A semiconductor device having a large storage capacity is provided. The semiconductor device includes an oxide provided over a substrate, a plurality of first conductors over the oxide, a first insulator that is provided over the plurality of first conductors and includes a plurality of openings overlapping with regions between the plurality of first conductors, a plurality of second insulators provided in the respective plurality of openings, a plurality of charge retention layers provided over the respective plurality of second insulators, a plurality of third insulators provided over the respective plurality of charge retention layers, and a plurality of second conductors provided over the respective plurality of third insulators.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 6, 2022
    Inventors: Tatsuya ONUKI, Takanori MATSUZAKI, Shunpei YAMAZAKI
  • Publication number: 20220318011
    Abstract: To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 6, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Tatsuya ONUKI
  • Patent number: 11462538
    Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Takanori Matsuzaki, Tomoaki Atsumi, Takahiko Ishizu
  • Publication number: 20220310616
    Abstract: A memory device occupying a small area is provided. In a memory cell including a reading transistor, a writing transistor, and a capacitor, the writing transistor is provided above the reading transistor. Alternatively, the reading transistor is provided above the writing transistor. An oxide semiconductor is used for a semiconductor layer where a channel of the writing transistor is formed. An oxide semiconductor is used for a semiconductor layer where a channel of the reading transistor is formed. Memory cells are arranged in a matrix.
    Type: Application
    Filed: August 11, 2020
    Publication date: September 29, 2022
    Inventors: Shuhei NAGATSUKA, Tatsuya ONUKI, Shunpei YAMAZAKI
  • Publication number: 20220293603
    Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 15, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Tatsuya ONUKI, Hajime KIMURA, Takayuki IKEDA, Shunpei YAMAZAKI
  • Patent number: 11423975
    Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Tatsuya Onuki
  • Publication number: 20220262858
    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
    Type: Application
    Filed: July 31, 2020
    Publication date: August 18, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO, Hiromichi GODO, Kazuki TSUDA, Hitoshi KUNITAKE
  • Publication number: 20220262438
    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
    Type: Application
    Filed: July 22, 2020
    Publication date: August 18, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO
  • Publication number: 20220246185
    Abstract: Provision of a novel semiconductor device. The semiconductor device includes a first control circuit including a first transistor using a silicon substrate for a channel; a second control circuit provided over the first control circuit, which includes a second transistor using a metal oxide for a channel; a memory circuit provided over the second control circuit, which includes a third transistor using a metal oxide for a channel; and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 4, 2022
    Inventors: Yuto YAKUBO, Seiya SAITO, Tatsuya ONUKI
  • Patent number: 11404107
    Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: August 2, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki
  • Publication number: 20220236785
    Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a power management unit, a CPU core, and a memory device, the power management unit includes a power switch and a power controller, and the memory device includes a working memory and a long-term memory storage portion. The power switch has a function of controlling supply of a power supply voltage to the CPU core and the memory device, and the power controller has a function of controlling operation of the power switch. The CPU core has a function of transmitting a timing of stopping the supply of the power supply voltage to the power controller, and the memory device has a function of saving data retained in the working memory to the long-term memory storage portion before the supply of the power supply voltage is stopped by the power switch. Transistors included in each of the power management unit and the CPU core are preferably Si transistors.
    Type: Application
    Filed: May 21, 2020
    Publication date: July 28, 2022
    Inventors: Shunpei YAMAZAKI, Takahiko ISHIZU, Tatsuya ONUKI, Hitoshi KUNITAKE