Patents by Inventor Tatsuya Ryoki

Tatsuya Ryoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838660
    Abstract: Since a failure related to an output from a sensor is not detected from an image signal and a failure of the sensor is not detected from an output from the sensor in a system including the sensor for abnormality detection, it is not possible to perform the abnormality detection and to indicate the abnormality to the outside of the system. An apparatus includes a pixel area including multiple pixels, multiple sensors, a processing unit that compares signals based on outputs from the multiple sensors with each other, an output unit that outputs information based on a result of comparison.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: December 5, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuya Itano, Tatsuya Ryoki, Yu Arishima, Taro Muraki
  • Patent number: 11770630
    Abstract: A photoelectric conversion apparatus includes a second substrate including a signal processing circuit configured to perform signal processing using machine learning on a signal output from the first substrate. The second substrate is disposed on the first substrate in a multilayer structure. The signal processing circuit is so disposed to overlap with a pixel array but not overlap with a light-shielded pixel area as seen in a plan view.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: September 26, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaki Sato, Masahiro Kobayashi, Tatsuya Ryoki, Kohichi Nakamura, Daisuke Kobayashi, Hiroaki Kameyama, Yasuhiro Oguro
  • Patent number: 11742373
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: August 29, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi
  • Patent number: 11652940
    Abstract: There is provide a photoelectric conversion device. In a first mode, a control unit performs control such that a signal output from each of a plurality of pixels is held in a corresponding holding unit. In a second mode, the control unit performs control of outputting a signal from the holding unit corresponding to a pixel in a first column and control of holding a signal based on a pixel in the first column in the holding unit corresponding to a pixel in a second column in parallel in the same period.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: May 16, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tatsuya Ryoki, Naoki Isoda
  • Patent number: 11637981
    Abstract: A photoelectric conversion apparatus having a first substrate and a second substrate overlaid on each other and including electrically conductive portions is provided. The first substrate includes a photoelectric conversion element, a first portion configured to form part of a first surface, a second portion which is included in an electrically conductive pattern closest to the first portion, and a third portion which is included in an electrically conductive pattern second closest to the first portion. The second substrate includes a fourth portion configured to form part of a second surface, and a circuit. In a planar view with respect to the first surface, an area of the first portion is smaller than an area of the second portion and larger than an area of a portion of the third portion overlaying the second portion.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 25, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Yamashita, Kazuhiro Saito, Tatsuya Ryoki, Yoshikazu Yamazaki
  • Patent number: 11592329
    Abstract: A photoelectric conversion apparatus includes a waveform shaping circuit, a reference circuit, and a counter. The waveform shaping circuit is configured to generate a first pulse signal based on a signal output from an avalanche diode. The reference circuit is configured to generate a second pulse signal without depending on incident light. The counter is connected to the waveform shaping circuit and the reference circuit to count a number of occurrences of a pulse signal. The pulse signal is based on at least one of the first pulse signal and the second pulse signal, and is input to the counter.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 28, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tatsuya Ryoki, Yukihiro Kuroda
  • Publication number: 20220294922
    Abstract: There is provide a photoelectric conversion device. In a first mode, a control unit performs control such that a signal output from each of a plurality of pixels is held in a corresponding holding unit. In a second mode, the control unit performs control of outputting a signal from the holding unit corresponding to a pixel in a first column and control of holding a signal based on a pixel in the first column in the holding unit corresponding to a pixel in a second column in parallel in the same period.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 15, 2022
    Inventors: Tatsuya Ryoki, Naoki Isoda
  • Publication number: 20220247948
    Abstract: A photoelectric conversion apparatus includes a second substrate including a signal processing circuit configured to perform signal processing using machine learning on a signal output from the first substrate. The second substrate is disposed on the first substrate in a multilayer structure. The signal processing circuit is so disposed to overlap with a pixel array but not overlap with a light-shielded pixel area as seen in a plan view.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 4, 2022
    Inventors: Masaki Sato, Masahiro Kobayashi, Tatsuya Ryoki, Kohichi Nakamura, Daisuke Kobayashi, Hiroaki Kameyama, Yasuhiro Oguro
  • Publication number: 20220247947
    Abstract: Since a failure related to an output from a sensor is not detected from an image signal and a failure of the sensor is not detected from an output from the sensor in a system including the sensor for abnormality detection, it is not possible to perform the abnormality detection and to indicate the abnormality to the outside of the system. An apparatus includes a pixel area including multiple pixels, multiple sensors, a processing unit that compares signals based on outputs from the multiple sensors with each other, an output unit that outputs information based on a result of comparison.
    Type: Application
    Filed: January 27, 2022
    Publication date: August 4, 2022
    Inventors: Tetsuya Itano, Tatsuya Ryoki, Yu Arishima, Taro Muraki
  • Publication number: 20220247921
    Abstract: A photoelectric conversion apparatus includes a first substrate including a pixel array including a plurality of pixels, and a second substrate disposed in a multilayer structure on the first substrate. The photoelectric conversion apparatus further includes a machine learning unit configured to execute processing using machine learning on a signal output from the pixel array, and a signal output unit configured to output a signal corresponding to temperature. Both the machine learning unit and the signal output unit are disposed on the second substrate.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 4, 2022
    Inventors: Tatsuya Ryoki, Tetsuya Itano
  • Patent number: 11385561
    Abstract: A driving apparatus is provided. The driving apparatus comprises a plurality of driving circuits configured to generate a current according to an inputted voltage. The plurality of driving circuits are formed on a single semiconductor chip, and each of the plurality of driving circuits comprises a plurality of output circuits configured to supply the current to a plurality of load elements arranged in at least one load element array.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: July 12, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tatsuya Suzuki, Tatsuya Ryoki
  • Patent number: 11067916
    Abstract: A driving apparatus comprising a driving circuit is provided. The driving circuit includes an output terminal to which the load element is connected, a current output circuit configured to supply a current to the load element, a voltage supply circuit configured to apply a voltage to the load element, a first signal line configured to control a timing at which the current output circuit starts supplying a current to the load element and a second signal line configured to control a timing at which the voltage supply circuit is turned off. The voltage supply circuit starts applying a voltage before the current output circuit supplies a current to the load element, and a timing at which the current output circuit starts supplying a current differs from a timing at which the voltage supply circuit turns off application of a voltage.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: July 20, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Suzuki, Masanobu Ohmura, Tatsuya Ryoki
  • Publication number: 20210167113
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi
  • Publication number: 20210123802
    Abstract: A photoelectric conversion apparatus includes a waveform shaping circuit, a reference circuit, and a counter. The waveform shaping circuit is configured to generate a first pulse signal based on a signal output from an avalanche diode. The reference circuit is configured to generate a second pulse signal without depending on incident light. The counter is connected to the waveform shaping circuit and the reference circuit to count a number of occurrences of a pulse signal. The pulse signal is based on at least one of the first pulse signal and the second pulse signal, and is input to the counter.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 29, 2021
    Inventors: Tatsuya Ryoki, Yukihiro Kuroda
  • Patent number: 10957732
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 23, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi
  • Publication number: 20210072661
    Abstract: A driving apparatus is provided. The driving apparatus comprises a plurality of driving circuits configured to generate a current according to an inputted voltage. The plurality of driving circuits are formed on a single semiconductor chip, and each of the plurality of driving circuits comprises a plurality of output circuits configured to supply the current to a plurality of load elements arranged in at least one load element array.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 11, 2021
    Inventors: Tatsuya Suzuki, Tatsuya Ryoki
  • Publication number: 20210063908
    Abstract: A driving apparatus comprising a driving circuit is provided. The driving circuit includes an output terminal to which the load element is connected, a current output circuit configured to supply a current to the load element, a voltage supply circuit configured to apply a voltage to the load element, a first signal line configured to control a timing at which the current output circuit starts supplying a current to the load element and a second signal line configured to control a timing at which the voltage supply circuit is turned off. The voltage supply circuit starts applying a voltage before the current output circuit supplies a current to the load element, and a timing at which the current output circuit starts supplying a current differs from a timing at which the voltage supply circuit turns off application of a voltage.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 4, 2021
    Inventors: Takanori Suzuki, Masanobu Ohmura, Tatsuya Ryoki
  • Publication number: 20200374481
    Abstract: A photoelectric conversion apparatus having a first substrate and a second substrate overlaid on each other and including electrically conductive portions is provided. The first substrate includes a photoelectric conversion element, a first portion configured to form part of a first surface, a second portion which is included in an electrically conductive pattern closest to the first portion, and a third portion which is included in an electrically conductive pattern second closest to the first portion. The second substrate includes a fourth portion configured to form part of a second surface, and a circuit. In a planar view with respect to the first surface, an area of the first portion is smaller than an area of the second portion and larger than an area of a portion of the third portion overlaying the second portion.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventors: Takanori Yamashita, Kazuhiro Saito, Tatsuya Ryoki, Yoshikazu Yamazaki
  • Patent number: 10778920
    Abstract: A photoelectric conversion apparatus having a first substrate and a second substrate overlaid on each other and including electrically conductive portions is provided. The first substrate includes a photoelectric conversion element, a first portion configured to form part of a first surface, a second portion which is included in an electrically conductive pattern closest to the first portion, and a third portion which is included in an electrically conductive pattern second closest to the first portion. The second substrate includes a fourth portion configured to form part of a second surface, and a circuit. In a planar view with respect to the first surface, an area of the first portion is smaller than an area of the second portion and larger than an area of a portion of the third portion overlaying the second portion.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 15, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Yamashita, Kazuhiro Saito, Tatsuya Ryoki, Yoshikazu Yamazaki
  • Publication number: 20190252444
    Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 15, 2019
    Inventors: Tatsuya Ryoki, Hirofumi Totsuka, Masahiro Kobayashi, Hideaki Ishino, Hiroaki Kobayashi