Abstract: A communication device sends use status data representing a state of use thereof to an external communication device. Receiving the use status data, the external communication device sends the first-mentioned communication device a releasing signal to release the first-mentioned communication device from inhibition of fulfillment of a function stored beforehand. In response to the releasing signal, the first-mentioned communication device reads and fulfills the stored function.

Abstract: A composite high-frequency component is designed to occupy a smaller area and a smaller volume when mounted in an apparatus, can be located in the apparatus with improved flexibility, and is able to operate without an impedance matching circuit. The composite high-frequency component includes a multilayer substrate, diodes constituting a high-frequency switch component, and a circuit base. External terminals for connection to a transmitting circuit, a receiving circuit and an antenna, external terminals for control and an external terminal for connection to ground potential are formed on an outer surface of the multilayer substrate. Strip lines and capacitors constituting the high-frequency switch and strip lines and capacitors constituting a low-pass filter circuit are formed in the multilayer substrate.

Abstract: A composite high frequency apparatus includes a high frequency filter and a high frequency switch which have a substantially reduced size and do not require an impedance matching circuit. The apparatus includes a multilayered base having an outer surface with a plurality of diodes, an external ground electrode, an external electrode for a transmission circuit, an external electrode for a receiving circuit, an external electrode for an antenna circuit and external electrodes for control terminals located thereon. A plurality of strip lines, capacitor electrodes and an external grounding electrode are located within the multilayered base.

Abstract: A composite high frequency apparatus includes a high frequency filter and a high frequency switch which have a substantially reduced size and do not require an impedance matching circuit. The apparatus includes a multilayered base having an outer surface with a plurality of diodes, an external ground electrode, an external electrode for a transmission circuit, an external electrode for a receiving circuit, an external electrode for an antenna circuit and external electrodes for control terminals located thereon. A plurality of strip lines, capacitor electrodes and an external grounding electrode are located within the multilayered base.

Abstract: A compact high frequency hybrid switch suitably operated in a diversity-type antenna system. A high frequency hybrid switch is comprised of: first to fourth ports; a first high frequency switch circuit for switching a connection established between the first port and the third port; and a second high frequency switch circuit for selecting one from two connections respectively established between the first port and the fourth port, and between the second port and the fourth port. The first and second high frequency switch circuits include respective series and parallel arrangements of diodes, capacitors and distributed constant signal lines which reduce the size and improve the reliability of the switch.

Abstract: The data processor related to the invention enables to designate whether the branch prediction mechanism itself should be activated or not for a conditional branch instruction, and the data processor enables to initialize branch history as required and also designates activation or inactivation of the branch prediction mechanism by setting a specific value to a specific bit of an exclusive usable register by software means. Also when a specific instruction is executed, the data processor automatically clears the branch history. As a result, in the event when the data processing efficiency is adversely declined by application of branch prediction mechanism or when monitoring external address bus, the branching prediction mechanism can be inactivated by setting the predetermined value to the exclusive usable register.

Abstract: A pipelined multi-stage data processor has a bypass circuit which is enabled when a memory reading request signal from the operand fetch stage and a memory writing request signal from the execution stage are simultaneously received by a control device with respect to an identical location in the memory. The bypass circuit operates to cause the write data to be written into the memory to be directly transferred to the fetch stage so that the memory reading operation is performed without actually accessing the memory.

Abstract: Conventional microprocessors access cache memory and external memory using a common data bus and share a single program counter. According to this invention, the cache memory and the external memory have corresponding program counters and separate data buses. The capacity to update the cache memory program counter concurrently with a cache memory access increases the speed of data processing.

Abstract: When a carry signal generated in an n-th bit is propagated to an (n+1)th bit, two n-MOS transistors (12.sub.n+1 and 13.sub.n+1) connected by a signal line (C.sub.n) are turned on to prompt transition of the signal line (C.sub.n) to a zero potential, thereby to increase the speed for propagating the carry signal. When the signal line (C.sub.n) propagates no carry signal, a p-MOS transistor (11.sub.n+1) is turned on to pull up the signal line (C.sub.n) to a supply potential V.sub.CC, thereby to stabilize the potential thereof.