Patents by Inventor Tatsuya Usuki

Tatsuya Usuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040201040
    Abstract: An electronic device which comprises one or more functional elements consisting of a high molecular weight material which has a steric structure containing one or more three-dimensionally disposed modifying functional groups, the steric structure on the high molecular weight material being known or predictable. In the electronic device, the high molecular weight material is a biopolymer, a synthetic polymer or a combination thereof, and the modifying functional groups are selected from the group consisting of positive hole-transporting functional groups, electron-transporting functional groups and a combination thereof. The electronic device includes a wide variety of devices such as diodes such as photodiodes and light-emitting diodes, capacitors, resistors and transistors such as bipolar transistors and FETs (field effect transistors).
    Type: Application
    Filed: February 2, 2004
    Publication date: October 14, 2004
    Inventors: Tsuyoshi Fujihara, Tatsuya Usuki, Shozo Fujita, Isao Saito
  • Publication number: 20040197070
    Abstract: A single-photon generator includes an exciton generation part including therein a quantum dot, an excitation part for generating an exciton in the exciton generator part, a recombination control part for controlling recombination timing of the exciton in the exciton generation part, and an optical window provided in the exciton generation part so as to pass a single photon formed as a result of recombination of the exciton, wherein the recombination control part causes, in the exciton generation part, recombination of the excitons at longer intervals than a recombination lifetime of a exciton molecule.
    Type: Application
    Filed: February 18, 2004
    Publication date: October 7, 2004
    Inventors: Kazuya Takemoto, Tatsuya Usuki, Motomu Takatsu
  • Patent number: 6462374
    Abstract: To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Usuki, Naoto Horiguchi
  • Publication number: 20020003255
    Abstract: To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.
    Type: Application
    Filed: March 22, 2001
    Publication date: January 10, 2002
    Applicant: Fujitsu Limited
    Inventors: Tatsuya Usuki, Naoto Horiguchi
  • Publication number: 20010002712
    Abstract: A tunneling insulating film is formed on the partial surface area of a semiconductor substrate. A floating gate electrode is formed on the tunneling insulating film. A gate insulating film covers the side wall of the floating gate electrode and a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A first control gate electrode is disposed on the gate insulating film over the side wall of the floating gate electrode and over a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A pair of impurity doped regions is formed in a surface layer of the semiconductor substrate on both sides of a gate structure including the floating gate structure and first control gate structure.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 7, 2001
    Inventors: Naoto Horiguchi, Tatsuya Usuki, Kenichi Goto
  • Patent number: 6195292
    Abstract: A source region and a drain region are formed in a surface layer of a semiconductor substrate on both sides of a channel region defined in the surface layer. A tunneling insulating film is formed on the channel region, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough. A floating gate electrode is formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction. A gate insulating film is formed over the channel region, covering the floating gate electrode. A control gate electrode is formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: February 27, 2001
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Usuki, Toshiro Futatsugi
  • Patent number: 5369288
    Abstract: In a semiconductor device, a channel layer of an undoped semiconductor material passes carriers therethrough ballistically, a carrier injection part injects the carriers into the channel layer with directivity to form a quantum mechanical wave of carriers, a carrier collection part provided on the channel layer recovers the carriers; a carrier drainage part provided on the channel layer absorbs the carriers that have been scattered; a carrier control part controls the flow of the carriers from the carrier injection part to the carrier collection part; and a potential control layer, provided adjacent to the channel layer, controls the potential level of the channel layer such that the potential level is uniform throughout the channel layer.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: November 29, 1994
    Assignee: Fujitsu Limited
    Inventor: Tatsuya Usuki