Patents by Inventor Tatsuya Yamada
Tatsuya Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080235498Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Applicant: ADVANTEST CORPORATIONInventor: TATSUYA YAMADA
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Publication number: 20080055955Abstract: A control apparatus for an AC-AC direct converter. The control apparatus includes a calculator providing a phase command ?* of an output voltage of the converter, a calculator providing a q-axis current iq by using output currents iu and iw and the phase command ?*, a detector detecting a pulsation component contained in the q-axis current iq, a calculator providing a phase correction magnitude ?cmp so as to decrease the pulsation component, and an adder/subtractor correcting the phase command ?* by using the correction magnitude ?cmp. This apparatus can decrease the output voltage distortion and low frequency torque pulsation and can suppress the increase of an output current without weakening a magnetic flux, even when the converter is operated in an overmodulation region.Type: ApplicationFiled: July 31, 2007Publication date: March 6, 2008Applicant: Fuji Electric FA Components & Systems Co., Ltd.Inventors: Yasuhiro Tamai, Tatsuya Yamada
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Publication number: 20070266290Abstract: There is provided a test apparatus that tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.Type: ApplicationFiled: January 10, 2007Publication date: November 15, 2007Applicant: Advantest CorporationInventors: Tatsuya Yamada, Masaru Doi, Shinya Satou
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Publication number: 20070257376Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: ApplicationFiled: July 16, 2007Publication date: November 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Publication number: 20070257708Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: ApplicationFiled: July 16, 2007Publication date: November 8, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Publication number: 20070124638Abstract: The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every test period, a plurality of edge generators that respectively generate an edge of a test signal to be supplied to the device under test based on the test pattern every cycle period of a reference clock that is used as a reference for an operation of this test apparatus, a selecting section that selects which edge generator generates each edge of a test signal to be output during the next cycle period based on a pattern of the edge generated during the current cycle period, and a test signal supplying section that supplies the test signal according to each edge generated from the selected edge generator to the device under test.Type: ApplicationFiled: October 27, 2006Publication date: May 31, 2007Applicant: Advantest CorporationInventor: Tatsuya Yamada
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Patent number: 7041718Abstract: The polyacetal resin composition contains about 0.01–10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01–10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.Type: GrantFiled: September 5, 2003Date of Patent: May 9, 2006Assignee: Polyplastics Co., Ltd.Inventors: Hatsuhiko Harashina, Hayato Kurita, Tatsuya Yamada
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Publication number: 20060055432Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.Type: ApplicationFiled: August 31, 2005Publication date: March 16, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
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Patent number: 6916184Abstract: The electrical connector housing contains a power distributor panel including a printed circuit board, one face of which carries conductors and semiconductor switching elements and the other face of which is adhered with a busbar. The electrical connector housing further contains a laminated-busbar unit connected to a power source circuit. A first tab is formed from one end of the busbar fixed to the power distributor panel, or by welding with the conductors, and is protruded beyond a first sidewall of the power distributor panel, while a second tab is formed from a busbar extending from the laminated-busbar unit. These tabs are connected by a relay system. The electrical connector housing thus manufactured can be assembled efficiently, its maintenance is easy, and the semiconductor switching elements used therein can be replaced easily.Type: GrantFiled: April 19, 2004Date of Patent: July 12, 2005Assignee: Sumitomo Wiring Systems, Ltd.Inventor: Tatsuya Yamada
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Publication number: 20050075429Abstract: The polyacetal resin composition contains about 0.01-10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01-10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.Type: ApplicationFiled: September 5, 2003Publication date: April 7, 2005Applicant: Polyplastics Co. Ltd.Inventors: Hatsuhiko Harashina, Hayato Kurita, Tatsuya Yamada
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Publication number: 20040235318Abstract: The electrical connector housing contains a power distributor panel including a printed circuit board, one face of which carries conductors and semiconductor switching elements and the other face of which is adhered with a busbar. The electrical connector housing further contains a laminated-busbar unit connected to a power source circuit. A first tab is formed from one end of the busbar fixed to the power distributor panel, or by welding with the conductors, and is protruded beyond a first sidewall of the power distributor panel, while a second tab is formed from a busbar extending from the laminated-busbar unit. These tabs are connected by a relay system. The electrical connector housing thus manufactured can be assembled efficiently, its maintenance is easy, and the semiconductor switching elements used therein can be replaced easily.Type: ApplicationFiled: April 19, 2004Publication date: November 25, 2004Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventor: Tatsuya Yamada
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Patent number: 6769083Abstract: A test pattern generator for generating a test pattern for testing electrical characteristics of an electrical device. The test pattern generator comprises a pattern memory (32), a pattern cache memory (54, 180 and 182), a vector memory (12), a read out controller (14 and 170), and a transfer controller (34 and 178). The pattern memory (32) stores the test pattern. The pattern cache memory (54, 180 and 182) stores the test pattern read out from the pattern memory (32). The vector memory (12) stores a vector instruction indicating an order of the test pattern to be generated. The read out controller (14 and 170) judges whether an address of the test pattern to be read out from the pattern memory (32) is to be jumped or not based on the vector instruction read out from the vector memory (12).Type: GrantFiled: November 10, 1999Date of Patent: July 27, 2004Assignee: Advantest CorporationInventors: Masaru Tsuto, Tatsuya Yamada
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Patent number: 6642289Abstract: The polyacetal resin composition contains about 0.01-10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01-10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.Type: GrantFiled: June 2, 1999Date of Patent: November 4, 2003Assignee: Polyplastics Co., Ltd.Inventors: Hatsuhiko Harashina, Hayato Kurita, Tatsuya Yamada
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Publication number: 20030158301Abstract: The polyacetal resin composition contains about 0.01-10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01-10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.Type: ApplicationFiled: June 2, 1999Publication date: August 21, 2003Inventors: HATSUHIKO HARASHINA, HAYATO KURITA, TATSUYA YAMADA
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Patent number: 6008105Abstract: The semiconductor masking device of the invention includes a first semiconductor mask for forming an interconnection on a semiconductor substrate and a second semiconductor mask for forming a resist pattern on an insulating film. The first semiconductor mask has three masking areas and the second semiconductor mask has two masking areas. Masking area intervals, that is, the distances between the three masking areas of the first semiconductor mask and the two masking areas of the second semiconductor mask, are all equal to one another.Type: GrantFiled: September 11, 1998Date of Patent: December 28, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takaaki Ukeda, Tatsuya Yamada, Yoshiaki Kato, Akio Miyajima
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Patent number: 5858578Abstract: The semiconductor masking device of the invention includes a first semiconductor mask for forming an interconnection on a semiconductor substrate and a second semiconductor mask for forming a resist pattern on an insulating film. The first semiconductor mask has three masking areas and the second semiconductor mask has two masking areas. Masking area intervals, that is, the distances between the three masking areas of the first semiconductor mask and the two masking areas of the second semiconductor mask, are all equal to one another.Type: GrantFiled: June 18, 1996Date of Patent: January 12, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takaaki Ukeda, Tatsuya Yamada, Yoshiaki Kato, Akio Miyajima
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Patent number: 5804879Abstract: An aluminum interconnection of the invention contains scandium as an impurity, so that the hardness of the interconnection in improved. Moreover, after a thin Al-Sc alloy film is formed, an annealing is performed 80 as to make the crystal grain larger than the width of the interconnection. The resulting Al interconnection has a high resistance against a stressmigration or electromigration, when a current stress in applied at a practical temperature in an LSI. This greatly contributes to the fabrication of a semiconductor device having a fine structure.Type: GrantFiled: May 24, 1996Date of Patent: September 8, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichi Ogawa, Hiroshi Nishimura, Tatsuya Yamada
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Patent number: 5768690Abstract: A radio communication device that performs time-sharing communication by switching between reception and transmission, comprises a circulator for guiding transmission signals to the antenna and reception signals from the antenna to the reception circuit. The output on the reception circuit side of the circulator is grounded via a terminal circuit which is operated during transmission and turned off during reception.Type: GrantFiled: October 10, 1995Date of Patent: June 16, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Yamada, Kyuichiro Aihara
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Patent number: D508682Type: GrantFiled: May 27, 2004Date of Patent: August 23, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Yamada, Kazuhiko Kurahashi, Toshihisa Inoue, Taizo Tomioka, Kazuo Shimokawa, Yoshiki Endo, Masahiro Urase, Osamu Usuda
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Patent number: D521952Type: GrantFiled: May 27, 2004Date of Patent: May 30, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Yamada, Kazuhiko Kurahashi, Toshihisa Inoue, Taizo Tomioka, Kazuo Shimokawa, Yoshiki Endo, Masahiro Urase, Osamu Usuda