Abstract: Disclosed is a highly practical composition for under layers which enables to form a good undercut profile without causing a intermixing layer between an upper layer resist and an under layer film in a bi-layer photoresist process. Also disclosed is a method for forming a resist pattern. Specifically disclosed is a composition for under layer organic films for forming a resist pattern having an undercut profile on a substrate by exposing and developing a bi-layer film through a mask which bi-layer film is formed on the substrate and composed of an under layer organic film and an upper layer positive resist film. Such a composition for under layer organic films comprises an alkali-soluble resin (A) obtained by condensing a phenol component (A1) which is a mixture of 3-methylphenol and 4-methylphenol and an aldehyde component (A2) comprising an aromatic aldehyde and formaldehyde, and a solvent (B).

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test.

Abstract: A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence for testing the device under test; an expanding section mat expands in a non-compression format the test instruction sequence read from the pattern memory; an instruction cache that caches the test instruction sequence which is expanded by the expanding section; a pattern generating section that sequentially reads instructions stored in the instruction cache and executes the same to generate a test pattern for the executed instruction; and a signal output section that generate a test signal based on the test pattern and provides the same to the device under test.

Abstract: There is provided a test apparatus that tests a device under test.

Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits.

Abstract: There is provided a test apparatus for testing a device under test.

Abstract: There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test.

Abstract: A test apparatus is provided. The test apparatus includes: a main memory that stores pattern data including at least one pattern bit defining a test signal provided to each of a plurality of terminals of the device under test; a pattern cache memory that caches the pattern data read from the main memory; a pattern generation control section that reads pattern data from the main memory and writes the same to the pattern cache memory; a pattern generating section that sequentially reads the pattern data stored in each cache entry of the pattern cache memory and outputs the same; and a channel circuit that generates a test signal corresponding to each of the plurality of terminals based on the pattern data outputted from the pattern generating section and provides the same to the device under test.

Abstract: A control apparatus for an AC-AC direct converter. The control apparatus includes a calculator providing a phase command ?* of an output voltage of the converter, a calculator providing a q-axis current iq by using output currents iu and iw and the phase command ?*, a detector detecting a pulsation component contained in the q-axis current iq, a calculator providing a phase correction magnitude ?cmp so as to decrease the pulsation component, and an adder/subtractor correcting the phase command ?* by using the correction magnitude ?cmp. This apparatus can decrease the output voltage distortion and low frequency torque pulsation and can suppress the increase of an output current without weakening a magnetic flux, even when the converter is operated in an overmodulation region.

Abstract: There is provided a test apparatus that tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every test period, a plurality of edge generators that respectively generate an edge of a test signal to be supplied to the device under test based on the test pattern every cycle period of a reference clock that is used as a reference for an operation of this test apparatus, a selecting section that selects which edge generator generates each edge of a test signal to be output during the next cycle period based on a pattern of the edge generated during the current cycle period, and a test signal supplying section that supplies the test signal according to each edge generated from the selected edge generator to the device under test.

Abstract: The polyacetal resin composition contains about 0.01–10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01–10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.

Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

Abstract: The electrical connector housing contains a power distributor panel including a printed circuit board, one face of which carries conductors and semiconductor switching elements and the other face of which is adhered with a busbar. The electrical connector housing further contains a laminated-busbar unit connected to a power source circuit. A first tab is formed from one end of the busbar fixed to the power distributor panel, or by welding with the conductors, and is protruded beyond a first sidewall of the power distributor panel, while a second tab is formed from a busbar extending from the laminated-busbar unit. These tabs are connected by a relay system. The electrical connector housing thus manufactured can be assembled efficiently, its maintenance is easy, and the semiconductor switching elements used therein can be replaced easily.

Abstract: The polyacetal resin composition contains about 0.01-10 parts by weight of a glyoxyldiureide compound per 100 parts by weight of polyacetal resin. The glyoxyldiureide compound includes glyoxyldiureide and its derivatives (metal salts etc.). Optionally, about 0.01-10 parts by weight of a basic nitrogen-containing compound is further added. The basic nitrogen-containing compound includes melamine, melamine resin, and polyamide resin. Further, an antioxidant may be further added. The above composition contributes to stability, particularly heat stability, of polyacetal resin and suppression of emission of formaldehyde.

Abstract: The electrical connector housing contains a power distributor panel including a printed circuit board, one face of which carries conductors and semiconductor switching elements and the other face of which is adhered with a busbar. The electrical connector housing further contains a laminated-busbar unit connected to a power source circuit. A first tab is formed from one end of the busbar fixed to the power distributor panel, or by welding with the conductors, and is protruded beyond a first sidewall of the power distributor panel, while a second tab is formed from a busbar extending from the laminated-busbar unit. These tabs are connected by a relay system. The electrical connector housing thus manufactured can be assembled efficiently, its maintenance is easy, and the semiconductor switching elements used therein can be replaced easily.