Abstract: Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: An circuit and method for minimizing clock skew in an integrated circuit. The circuit is configured as a combination of delay elements and connection matrices that by connecting input and output pins in the connection matrix the circuit designer can select the required delay value. The connection matrices are defined in the circuit synthesis process as non routable areas therefore the programmable delay cells are programed after the circuit design is complete without requiring the circuit to be re routed. By inserting standard programmable delay cells in the clock tree the circuit designer can build in adjustable compensation for a wide range of clock skew.