Abstract: Disclosed is a transmission gate circuit including a control voltage generating circuit, a high voltage transmission circuit and a low voltage transmission circuit. The high and low voltage transmission circuits are coupled between an input terminal and an output terminal The control voltage generating circuit generates two voltage groups according to an input voltage of the input terminal and an enable voltage and thereby controls the high and low voltage transmission circuits with the two voltage groups respectively. When the enable voltage is high, one voltage group includes identical voltages while a difference between any of the identical voltages and any voltage of the other voltage group is not higher than a predetermined voltage; when the enable voltage is low, each voltage group includes decremental voltages. The high/low voltage transmission circuit is turned on when the enable voltage is high and the input voltage is high/low.

Abstract: Disclosed is an inverter capable of withstanding a high voltage. The inverter includes a control voltage generating circuit, a high voltage transmission circuit, and a low voltage transmission circuit. The control voltage generating circuit generates a first group of control voltages and a second group of control voltages according to an input voltage, in which one group includes decrement voltages and the other group includes identical voltages. The high/low voltage transmission circuit is coupled between a high/low voltage terminal and an output terminal, wherein when the input voltage is low/high, the high/low voltage transmission circuit is turned on according to the first/second group of control voltages so that an output voltage of the output terminal is equal to a high/low voltage of the high/low voltage terminal.

Abstract: A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.

Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

Abstract: The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.

Abstract: A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.

Abstract: A trigger circuit, including: an input terminal, an output terminal, a control circuit and a logic circuit. The control circuit is coupled to the input terminal and the output terminal. The control circuit receives an input voltage from the input terminal and an output voltage from the output terminal, and generates a plurality of reference voltages at least according to the input voltage and the output voltage. The logic circuit is coupled to the control circuit and the output terminal. When the input voltage is converted into a second voltage value from a first voltage value, the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage into the first voltage value from the second voltage value.

Abstract: An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N?1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N?1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic low level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.

Abstract: An ESD protection device includes a detection circuit and a clamping circuit. The detection circuit is configured to output a first control signal and a second control signal according to a first voltage and a second voltage that is different from the first voltage, in which if an ESD event occurs, the detection circuit is configured to perform an inverse operation according to the second voltage, in order to generate the first control signal and the second control signal. The clamping circuit is configured to be turned on according to the first control signal and the second control signal, in order to provide a discharging path for a current associated with the ESD event.

Abstract: The present invention discloses a current-mirror-based electrostatic discharge (ESD) clamping circuit comprising: a first power terminal; a second power terminal; a current-mirror-based ESD detector; a driver; and an ESD clamping element. The current-mirror-based ESD detector includes: a resistor coupled between the first power terminal and a detection-output-terminal; a semiconductor capacitor coupled between the detection-output-terminal and an ESD triggered current mirror; and the ESD triggered current mirror operable to electrically connect the semiconductor capacitor and/or the detection-output-terminal with the second power terminal according to the level of a driving signal under an ESD operation. The driver is operable to generate the driving signal according to the voltages of the detection-output-terminal and the first and second power terminals.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic low level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

Abstract: The disclosure provides an ESD protection circuit. The ESD protection circuit comprises: a clamping unit, a driving unit, a resistance unit, a switch unit, and a capacitance unit. The clamping device is coupled between a first power source and a second power source. The driving unit is coupled between the clamping device and a reference node. The resistance unit is coupled between the first power source and the reference node. The switch unit is coupled to the driving unit via the reference node. The capacitance unit is coupled between the switch unit and the second power source. Under a normal operation condition, the driving unit controls the switch unit to be in an un-conducting status. Under an ESD condition, the driving unit controls the switch unit to be in a conducting status.

Abstract: An ESD protection circuit includes a plurality of resistors, at least a capacitor, a driving circuit and an ESD clamping device, wherein a first node of each resistor is connected to a first supply voltage, and a second node of each of at least a portion of the resistors is selectively connected to an input node via a corresponding switch respectively, and a first node of the capacitor is connected to a second supply voltage, and a second node of the capacitor is connected to the input node; the driving circuit is arranged to generate a driving signal according to a voltage on the input node; and the ESD clamping device is coupled to the driving circuit, and connected between the first supply voltage and the second supple voltage, and the ESD clamping device is arranged to selectively bypass an ESD current according to the driving signal.

Abstract: An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.