Patents by Inventor Tazrien Kamal
Tazrien Kamal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9318373Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).Type: GrantFiled: April 19, 2013Date of Patent: April 19, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: David M Rogers, Mimi X Qian, Kwadwo A Appiah, Mark Randolph, Michael A VanBuskirk, Tazrien Kamal, Hiroyuki Kinoshita, Yi He, Wei Zheng
-
Patent number: 8673716Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.Type: GrantFiled: April 8, 2002Date of Patent: March 18, 2014Assignee: Spansion LLCInventors: Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun
-
Publication number: 20130237022Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).Type: ApplicationFiled: April 19, 2013Publication date: September 12, 2013Applicant: SPANSION LLCInventors: David M Rogers, Mimi X Qian, Kwadwo A Appiah, Mark Randolph, Michael A VanBuskirk, Tazrien Kamal, Hiroyuki Kinoshita, Yi HE, Wei Zheng
-
Patent number: 8445966Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).Type: GrantFiled: December 20, 2006Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: David M. Rogers, Mimi X. Qian, Kwadwo A. Appiah, Mark Randolph, Michael A. VanBuskirk, Tazrien Kamal, Hiroyuki Kinoshita, Yi He, Wei Zheng
-
Patent number: 7972948Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.Type: GrantFiled: September 13, 2010Date of Patent: July 5, 2011Assignee: Spansion LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
-
Publication number: 20100330762Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width.Type: ApplicationFiled: September 13, 2010Publication date: December 30, 2010Applicant: SPANSION LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
-
Patent number: 7811915Abstract: A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.Type: GrantFiled: March 14, 2008Date of Patent: October 12, 2010Assignee: Spansion LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
-
Publication number: 20080157187Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width.Type: ApplicationFiled: March 14, 2008Publication date: July 3, 2008Applicant: SPANSION LLCInventors: Weidong QIAN, Mark T. RAMSBEY, Tazrien KAMAL
-
Publication number: 20080151590Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: David M. Rogers, Mimi X. Qian, Kwadwo A. Appiah, Mark Randolph, Michael A. VanBuskirk, Tazrien Kamal, Hiroyuki Kinoshita, Yi He, Wei Zheng
-
Patent number: 7297592Abstract: A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.Type: GrantFiled: August 1, 2005Date of Patent: November 20, 2007Assignee: Spansion LLCInventors: Minh Van Ngo, Arvind Halliyal, Tazrien Kamal, Hidehiko Shiraiwa, Rinji Sugino, Dawn Hopper, Pei-Yuan Gao
-
Patent number: 7176113Abstract: The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.Type: GrantFiled: June 7, 2004Date of Patent: February 13, 2007Assignee: Spansion LLCInventors: Nga-Ching Alan Wong, Weidong Qian, Sameer Haddad, Mark Randolph, Mark Ramsbey, Tazrien Kamal
-
Patent number: 7163860Abstract: The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.Type: GrantFiled: May 6, 2003Date of Patent: January 16, 2007Assignee: Spansion LLCInventors: Tazrien Kamal, Yun Wu, Mark Ramsbey, Jean Yee-Mei Yang, Arvind Halliyal, Rinji Sugino, Hidehiko Shiraiwa, Fred T K Cheung
-
Patent number: 7060554Abstract: A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.Type: GrantFiled: July 11, 2003Date of Patent: June 13, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Mark Ramsbey, Tazrien Kamal, Pei Yuan Gao
-
Patent number: 7053446Abstract: A memory includes a semiconductor substrate and a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the wordline.Type: GrantFiled: June 8, 2004Date of Patent: May 30, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Kashmir S. Sahota, Tazrien Kamal, Mark T. Ramsbey
-
Patent number: 7033957Abstract: Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.Type: GrantFiled: February 5, 2003Date of Patent: April 25, 2006Assignee: FASL, LLCInventors: Hidehiko Shiraiwa, Tazrien Kamal, Mark Ramsbey, Inkuk Kang, Jaeyong Park, Rinji Sugino, Jean Y. Yang, Fred T K Cheung, Arvind Halliyal, Amir H. Jafarpour
-
Patent number: 7023046Abstract: Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 ? to 600 ?, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.Type: GrantFiled: July 11, 2003Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Angela Hui, Ning Cheng, Jeyong Park, Jean Yee-Mei Yang, Robert A. Huertas, Tazrien Kamal, Pei-Yuan Gao, Tyagamohan Gottipati
-
Patent number: 7018896Abstract: A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.Type: GrantFiled: April 5, 2004Date of Patent: March 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Minh V. Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park, Ning Cheng, Jeff P. Erhardt, Clarence B. Ferguson, Jeffrey A. Shields, Angela T. Hui, Robert A. Huertas, Tyagamohan Gottipati
-
Patent number: 7018868Abstract: The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.Type: GrantFiled: February 2, 2004Date of Patent: March 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Jean Y. Yang, Jeff P. Erhardt, Cyrus Tabery, Weidong Qian, Mark T. Ramsbey, Jaeyong Park, Tazrien Kamal
-
Patent number: 6995423Abstract: A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A P+ polysilicon gate electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells within the nitride layer are erased simultaneously.Type: GrantFiled: June 28, 2004Date of Patent: February 7, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Wei Zheng, Chi Chang, Tazrien Kamal
-
Patent number: 6969886Abstract: A SONOS flash memory device, including a semiconductor substrate; an ONO structure formed on the semiconductor substrate, the ONO structure including a bottom oxide layer, a dielectric charge storage layer and a top oxide layer, the bottom oxide layer having a super-stoichiometric oxygen content and an oxygen vacancy content of about 1010/cm2 or less, wherein the bottom oxide layer exhibits a reduced charge leakage relative to a bottom oxide layer having a stoichiometric or sub-stoichiometric oxygen content and a greater number of oxygen vacancies. In one embodiment, the bottom oxide layer has an oxygen vacancy content of substantially zero.Type: GrantFiled: July 12, 2004Date of Patent: November 29, 2005Assignee: FASL, LLCInventors: Jaeyong Park, Hidehiko Shiraiwa, Arvind Halliyal, Jean Y. Yang, Inkuk Kang, Tazrien Kamal, Amir H. Jafarpour