Abstract: A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.

Abstract: A charge trapping dielectric memory device. The memory device includes a gate electrode disposed over a dielectric stack that includes a dielectric charge trapping layer. The gate electrode has a work function of about 4.6 eV to about 5.2 eV.

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

Abstract: A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

Abstract: A method of manufacturing an integrated circuit includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer and a gate dielectric layer over the semiconductor substrate. Bitlines are implanted closely in the semiconductor substrate and annealed using a rapid thermal anneal. Wordlines and gates are formed and source/drain junctions are implanted in the semiconductor substrate. An interlayer dielectric layer is deposited and the integrated circuit completed.

Abstract: A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.

Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

Abstract: A liquid cleaning composition and method for removal of photoresist including an aliphatic alcohol. Preferably, the alcohol is isopropyl alcohol. Additionally, an alcohol/base mixture can be used to remove photoresist, rather than alcohol used alone. Preferably, the alcohol is isopropyl alcohol, while the aqueous base is ammonium hydroxide. The temperature conditions range from about 25 degrees C. to about 70 degrees C. The pressure conditions range from about 14 pounds per square inch to about 100 pounds per square inch.

Abstract: A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.

Abstract: A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.

Abstract: One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third