Patents by Inventor Te-Chang Hsu

Te-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365710
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Patent number: 10777657
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Publication number: 20200279917
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200235224
    Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
    Type: Application
    Filed: March 31, 2020
    Publication date: July 23, 2020
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 10700163
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200194058
    Abstract: The present invention provides a static random access memory (SRAM), the SRAM includes a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern at least includes a first gate structure, a second gate structure and a third gate structure, arranged along a first direction, wherein the second gate structure and the third gate structure are parallel to the first gate structure, and a gap is disposed between the second gate structure and the third gate structure, and wherein the first gate structure is composed of a first elongated structure, a second elongated structure and a curved structure disposed between the first elongated structure and the second elongated structure, and wherein the curved structure is aligned with the gap along a second direction, and an interconnection contact structure disposed between the first gate structure and the second gate structure, and arranged along the first direction.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Te-Chang Hsu, Cheng-Pu Chiu, Chun-Jen Huang, Cheng-Yeh Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Publication number: 20200185525
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10651290
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 10644381
    Abstract: An antenna structure includes a housing, a first feed source, a first radiator, a second radiator, and a second feed source. The housing includes a first radiating portion. The first feed source feeds current to the first radiating portion and the first radiating portion activates a first mode to generate radiation signals in a first frequency band. The first radiator is positioned in the housing. The first radiating portion further couples the current to the first radiator and the first radiator activates a second mode to generate radiation signals in a second frequency band. The second radiator is positioned in a space formed by the first radiator. The second feed source feeds current to the second radiator and the second radiator activates a third mode to generate radiation signals in a third frequency band.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: May 5, 2020
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Wei-Xuan Ye, Wen-Chang Hsu, Te-Chang Lin
  • Publication number: 20200127089
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: November 18, 2018
    Publication date: April 23, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200105933
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 2, 2020
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10608113
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10389030
    Abstract: An antenna structure includes a feed portion, a high-frequency radiating portion, a low-frequency radiating portion, an extension portion, and a switching unit. The high-frequency radiating portion is electrically connected to the feed portion. The low-frequency radiating portion is electrically connected to the high-frequency radiating portion. The extension portion is electrically connected to the feed portion and the high-frequency radiating portion. The switching unit is electrically connected to the extension portion to control the extension portion to be in one of an open-circuit state and a short-circuit state.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cho-Kang Hsu, Te-Chang Lin
  • Publication number: 20190140077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 10283415
    Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
  • Publication number: 20190103492
    Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 4, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Cheng-Pu Chiu, Pei-Yu Chen, Shih-Min Lu, Ming-Yueh Tsai, Yung-Sung Lin, Te-Chang Hsu, Chih-Yi Wang, Chi-Hsuan Cheng, Sheng-Chen Chung, Yao-Jhan Wang
  • Patent number: 10249729
    Abstract: A method for fabricating a semiconductor device. After forming SiGe epitaxial layer within the Core_p region, the hard mask is removed. A contact etch stop layer (CESL) is deposited on the composite spacer structure and the epitaxial layer. An ILD layer is deposited on the CESL. The ILD layer is polished to expose a top surface of the dummy gate. The dummy gate and a first portion of the first nitride-containing layer of the composite spacer structure are removed, thereby forming a gate trench and exposing the first gate dielectric layer. The first gate dielectric layer is removed from the gate trench, and a second portion of the first nitride-containing layer and the oxide layer are removed from the composite spacer structure, while leaving the second nitride-containing layer intact.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Hsien Chen, Chun-Chia Chen, Yao-Jhan Wang, Chih-wei Yang, Te-Chang Hsu
  • Publication number: 20190080968
    Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.
    Type: Application
    Filed: September 10, 2017
    Publication date: March 14, 2019
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
  • Publication number: 20190058050
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
    Type: Application
    Filed: September 20, 2017
    Publication date: February 21, 2019
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang, Chun-Jen Huang
  • Patent number: 10211107
    Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang