Patents by Inventor Te-Hsien Hsieh
Te-Hsien Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369024Abstract: In some embodiments, the present disclosure relates to a method of performing an etching process. The method includes generating a plasma within a plasma chamber in communication with a processing chamber. Ions from the plasma are accelerated toward a workpiece within the processing chamber to generate an ion beam. The ion beam performs an etching process that etches a material on the workpiece. A by-product from the etching process is moved to directly below one or more baffles within the processing chamber.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Te-Hsien Hsieh, Lee-Chuan Tseng
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Publication number: 20230361024Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Inventors: Te-Hsien Hsieh, Yu-Hsing Chang, Yi-Min Chen
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Patent number: 11776901Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.Type: GrantFiled: March 10, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Hsien Hsieh, Yu-Hsing Chang, Yi-Min Chen
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Patent number: 11751406Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.Type: GrantFiled: August 3, 2021Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Hsien Hsieh, Tzu-Yu Chen, Kuo-Chi Tu, Yuan-Tai Tseng
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Publication number: 20230253435Abstract: The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.Type: ApplicationFiled: May 3, 2022Publication date: August 10, 2023Inventors: Yung-Chang Chang, Shih-Wei Lin, Te-Hsien Hsieh, Jung-I Lin
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Patent number: 11690232Abstract: A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.Type: GrantFiled: May 28, 2020Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Te-Hsien Hsieh, Yuan-Tai Tseng
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Publication number: 20220293515Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.Type: ApplicationFiled: March 10, 2021Publication date: September 15, 2022Inventors: Te-Hsien Hsieh, Yu-Hsing Chang, Yi-Min Chen
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Publication number: 20220148856Abstract: In some embodiments, the present disclosure relates to an etching apparatus. The etching apparatus includes a substrate holder disposed within a processing chamber and having a workpiece reception surface configured to hold a workpiece. A lower surface of the processing chamber has a first region that is directly below the workpiece reception surface and that is configured to receive a byproduct from an etching process. A baffle extends outward from a sidewall of the processing chamber at a vertical position between the substrate holder and the lower surface of the processing chamber. The baffle covers a second region of the lower surface. A byproduct redistributor is configured to move the byproduct from the first region of the lower surface to the second region of the lower surface that is directly below the baffle.Type: ApplicationFiled: January 27, 2022Publication date: May 12, 2022Inventors: Te-Hsien Hsieh, Lee-Chuan Tseng
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Patent number: 11239060Abstract: In some embodiments, the present disclosure relates to an ion beam etching apparatus. The ion beam etching apparatus includes a substrate holder disposed within a processing chamber and a plasma source in communication with the processing chamber. A vacuum pump is coupled to the processing chamber by way of an inlet. One or more baffles are arranged between the substrate holder and a lower surface of the processing chamber. A by-product redistributor is configured to move a by-product from an etching process from outside of the one or more baffles to directly below the one or more baffles.Type: GrantFiled: May 29, 2018Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Hsien Hsieh, Lee-Chuan Tseng
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Publication number: 20210375993Abstract: A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: Te-Hsien Hsieh, Yuan-Tai Tseng
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Publication number: 20210366987Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: Te-Hsien Hsieh, Tzu-Yu Chen, Kuo-Chi Tu, Yuan-Tai Tseng
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Patent number: 11088203Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.Type: GrantFiled: September 19, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Hsien Hsieh, Tzu-Yu Chen, Kuo-Chi Tu, Yuan-Tai Tseng
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Publication number: 20210036057Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.Type: ApplicationFiled: September 19, 2019Publication date: February 4, 2021Inventors: Te-Hsien Hsieh, Tzu-Yu Chen, Kuo-Chi Tu, Yuan-Tai Tseng
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Publication number: 20190371574Abstract: In some embodiments, the present disclosure relates to an ion beam etching apparatus. The ion beam etching apparatus includes a substrate holder disposed within a processing chamber and a plasma source in communication with the processing chamber. A vacuum pump is coupled to the processing chamber by way of an inlet. One or more baffles are arranged between the substrate holder and a lower surface of the processing chamber. A byproduct redistributor is configured to move a byproduct from an etching process from outside of the one or more baffles to directly below the one or more baffles.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: Te-Hsien Hsieh, Lee-Chuan Tseng
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Patent number: 9785046Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.Type: GrantFiled: January 21, 2015Date of Patent: October 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
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Patent number: 9747404Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: GrantFiled: July 23, 2015Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
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Publication number: 20170024506Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
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Publication number: 20160147140Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.Type: ApplicationFiled: January 21, 2015Publication date: May 26, 2016Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
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Patent number: 9262820Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.Type: GrantFiled: May 19, 2014Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee
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Publication number: 20150332449Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Te-Hsien HSIEH, Ming-Jui CHEN, Cheng-Te WANG, Jing-Yi LEE