Patents by Inventor Te-Hsin Chiu

Te-Hsin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009364
    Abstract: In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Meng-Hung Shen, Jiann-Tyng Tzeng
  • Publication number: 20240186241
    Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
    Type: Application
    Filed: February 14, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Jiun-Wei LU
  • Publication number: 20240170551
    Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han LIN, Wei-Cheng WU, Te-Hsin CHIU
  • Publication number: 20240145475
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: SHIH-WEI PENG, TE-HSIN CHIU, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Patent number: 11950413
    Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-? dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-?) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one ?m2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu
  • Patent number: 11948974
    Abstract: A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng
  • Publication number: 20240105601
    Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 28, 2024
    Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU
  • Patent number: 11943921
    Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 11942469
    Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang
  • Patent number: 11935830
    Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Jiun-Wei Lu
  • Patent number: 11923427
    Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Wei-Cheng Wu, Te-Hsin Chiu
  • Patent number: 11923369
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai, Jiann-Tyng Tzeng
  • Patent number: 11916070
    Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Kam-Tou Sio, Shang-Wei Fang, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11894375
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes an upper portion and a lower portion, and the first conductive line crosses the first gate between the upper portion and the lower portion.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11854786
    Abstract: An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu
  • Publication number: 20230411389
    Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 21, 2023
    Inventors: Te-Hsin CHIU, Kam-Tou SIO, Shang-Wei FANG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20230411300
    Abstract: A method of forming an integrated circuit (IC) package includes constructing a first power distribution structure on a first die included in the IC package, thereby electrically connecting the first power distribution structure to a second power distribution structure positioned on a back side of the first die, and bonding a third power distribution structure to the first power distribution structure, the third power distribution structure being positioned on a back side of a second die.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 21, 2023
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG
  • Publication number: 20230402461
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Te-Hsin CHIU, Wei-Cheng LIN, Wei-An LAI, Jiann-Tyng TZENG
  • Patent number: 11842994
    Abstract: A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between corresponding ends of remnant portion of gate patterns are expanded.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20230395503
    Abstract: A method of making an integrated includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 7, 2023
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Wei-An LAI, Ching-Wei TSAI, Jiann-Tyng TZENG