Patents by Inventor Te-Hsun Hsu

Te-Hsun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111180
    Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a substrate; forming a second dielectric layer on the first dielectric layer; using a photomask to apply a photoresist to cover a first part of the second dielectric layer; removing a second part of the second dielectric layer while retaining the first part of the second dielectric layer; and removing the photoresist. The first part of the second dielectric layer covers a first part of the first dielectric layer in a first area. The second part of the second dielectric layer covers a second part of the first dielectric layer in a second area. The first area is corresponding to a memory device. The second area is corresponding to a logic device.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 15, 2021
    Inventor: Te-Hsun Hsu
  • Patent number: 10192875
    Abstract: A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed. The stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor??(1).
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: January 29, 2019
    Assignee: eMemory Technology Inc.
    Inventor: Te-Hsun Hsu
  • Patent number: 9640262
    Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 2, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Chun-Hsiao Li, Hsuen-Wei Chen
  • Publication number: 20170040330
    Abstract: A non-volatile memory including following elements is provided. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor. The stress-releasing transistor has a stress release ratio represented by formula (1). A lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. An upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 9, 2017
    Applicant: eMemory Technology Inc.
    Inventor: Te-Hsun Hsu
  • Patent number: 9508447
    Abstract: A non-volatile memory including a substrate, a floating gate transistor, a select transistor and a stress-releasing transistor. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: November 29, 2016
    Assignee: eMemory Technology Inc.
    Inventor: Te-Hsun Hsu
  • Patent number: 9391083
    Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 12, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Hsuen-Wei Chen, Mu-Ying Tsao, Ying-Je Chen
  • Publication number: 20160104712
    Abstract: A one time programmable (OTP) non-volatile memory including a substrate, a switch device and a fuse structure is provided. The switch device is disposed on the substrate. The fuse structure includes a conductive layer, a spacer and a plug. The conductive layer is coupled to a terminal of the switch device. The spacer is disposed on a sidewall of the conductive layer. The plug is disposed on the conductive layer and covers the spacer. An overlap area of an overlap portion between the plug and a top surface of the conductive layer is smaller than a top view area of the plug.
    Type: Application
    Filed: September 2, 2015
    Publication date: April 14, 2016
    Inventor: Te-Hsun Hsu
  • Publication number: 20160104711
    Abstract: A non-volatile memory including a substrate, a floating gate transistor, a select transistor and a stress-releasing transistor. The floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. The stress-releasing transistor is located between the floating gate transistor and the select transistor.
    Type: Application
    Filed: September 2, 2015
    Publication date: April 14, 2016
    Inventor: Te-Hsun Hsu
  • Publication number: 20160013199
    Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.
    Type: Application
    Filed: May 22, 2015
    Publication date: January 14, 2016
    Inventors: Te-Hsun Hsu, Chun-Hsiao Li, Hsuen-Wei Chen
  • Patent number: 9147690
    Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 29, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Wen-Hao Lee
  • Publication number: 20150243669
    Abstract: Provided is a memory device including a control gate, floating gates, an inter-gate insulating layer and a select gate. The control gate is disposed on a substrate. The floating gates are disposed between the control gate and the substrate, wherein a width of each floating gate is greater than a width of the control gate. The inter-gate insulating layer is disposed between the control gate and each of the floating gates. The select gate is disposed on the substrate adjacent to the control gate.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventor: Te-Hsun Hsu
  • Patent number: 9099392
    Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 4, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Te-Hsun Hsu, Hsin-Ming Chen, Wen-Hao Ching, Wei-Ren Chen
  • Publication number: 20150194434
    Abstract: A method of forming a memory device is provided. A first conductive layer is formed on a substrate. The first conductive layer is patterned to form at least two trenches extending along a first direction therein. An insulating layer is formed on surfaces of the trenches and on a surface of the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form at least one control gate extending along a second direction different from the first direction. The first conductive layer is patterned to form at least one floating gate below the control gate and to form a select gate adjacent to the control gate.
    Type: Application
    Filed: July 29, 2014
    Publication date: July 9, 2015
    Inventor: Te-Hsun Hsu
  • Patent number: 9018691
    Abstract: A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: April 28, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Chih-Hsin Chen
  • Publication number: 20150091074
    Abstract: A nonvolatile memory structure included a P substrate, an N well in the P substrate, and a PMOS storage transistor. The PMOS storage transistor includes a floating gate and an auxiliary gate disposed in close proximity to the floating gate. The floating gate and the auxiliary gate are disposed directly on the same floating gate channel of the PMOS storage transistor. A gap is provided between the auxiliary gate and the floating gate such that the auxiliary gate and the floating gate are separated from each other at least directly above the floating gate channel.
    Type: Application
    Filed: September 4, 2014
    Publication date: April 2, 2015
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Hsuen-Wei Chen, Mu-Ying Tsao, Ying-Je Chen
  • Patent number: 8958245
    Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang
  • Patent number: 8941167
    Abstract: An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 27, 2015
    Assignee: Ememory Technology Inc.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Shih-Chen Wang, Hsin-Ming Chen, Ching-Sung Yang
  • Publication number: 20140242763
    Abstract: A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.
    Type: Application
    Filed: May 14, 2014
    Publication date: August 28, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Chih-Hsin Chen
  • Patent number: 8787092
    Abstract: The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: July 22, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Hsin-Ming Chen
  • Patent number: 8779520
    Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: July 15, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Wen-Hao Lee