Abstract: The present disclosure provides a vertical-cavity surface-emitting laser, structured light module, terminal comprising the structured light module, and method for projecting the structured light thereof. The structured light module includes a plurality of light sources and a single diffractive optical element (DOE); wherein the plurality of light sources simultaneously emit a plurality beams of invisible light to the single DOE, wherein the single DOE has a pseudo-random optical pattern groove, wherein the invisible light of each light source passes through the DOE and emits a beam of spectral encoded structured light, and the beam of structured light comprises a pattern corresponding to the pseudo-random optical pattern groove. The DOE projects an overall structured light that is formed by superimposing a plurality of beams of structured light, and there is an offset between patterns of different beams of structured light.

Abstract: The invention provides a method for modeling and compensating for the spindle's radial thermal drift error in a horizontal CNC lathe, which belongs to the field of error compensation technology of CNC machine tools. Firstly, the thermal drift error of two points in the radial direction of the spindle and the corresponding temperature of the key points are tested; then the thermal inclination angle of the spindle is obtained based on the thermal tilt deformation mechanism of the spindle, and the correlation between the thermal inclination angle and the temperature difference between the left and right sides of the spindle box is analyzed. According to the positive or negative thermal drift error of the two points that have been measured and the elongation or shortening of the spindle box on the left and right sides, the thermal deformation of the spindle is then classified and the thermal drift error model under various thermal deformation attitudes is then established.

Abstract: A fingerprint image enhancement method, comprising: receiving a fingerprint image; computing a horizontal variation image and a vertical variation image of the fingerprint image (300); computing a weighted image, wherein a weighted value of a first pixel corresponding to a finger ridge in the weighted image is greater than a weighted value of a second pixel corresponding to a finger valley (304); multiplying the horizontal variation image with the weighted image to generate a weighted horizontal variation image, and multiplying the vertical variation image with the weighted image to generate a weighted vertical variation image (306); computing a fingerprint orientation image according to the weighted horizontal variation image and the weighted vertical variation image (308); and performing fingerprint image enhancement on the fingerprint image according to the fingerprint orientation image (310).

Abstract: A background subtraction method includes: obtaining a first background image corresponding to a first object, wherein the first object has a first reflectivity; obtaining a second background image corresponding to a second object, wherein the second object has a second reflectivity, and the first reflectivity is different from the second reflectivity; calculating a plurality of relative values of the first background image relative to the second background image so as to obtain a mask image; obtaining a target image; subtracting the second background image from the target image so as to obtain a first background-removed image; and calculating and outputting a second background-removed image according to the first background image, the second background image, the first background-removed image and the mask image.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.

Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.

Abstract: An electronic device is provided. The An electronic device comprises a near field communication (NFC) circuit for transmitting a set of near field communication differential signals including a first differential signal and a second differential signal; a housing including a conducting portion with a ground point, a first side and a second side opposite to the first side; and two conductive arms. A current loop is formed by the conductive arm and the conducting portion, and a potential of the ground point is equal to a median potential of the current loop.

Abstract: An antenna module is provided. The antenna module includes a circuit board, a conductive layer, and a spiral coil. The circuit board has a first surface and a second surface opposite to each other. The circuit board further includes a first block and a second block connected to each other. The conductive layer is disposed on the first block. The spiral coil is disposed in the second block of the circuit board. The conductive layer at least partially surrounds the spiral coil.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

Abstract: An LED-based ultraviolet illuminator includes an exposure module, an illumination module, a light mixing system, a beam splitter, an optical lens system, a sensor and a controller. The exposure module includes light sources that emit UV light at different wavelengths. The illumination module includes at least one light source that emits visible light for alignment. The sensor detects light energy of a portion of the UV light at each wavelength. The controller is operably connected to the exposure module and the sensor, and configured to operate in a plurality of exposure modes according to which the controller turns on or off the UV-LED light sources of the exposure module. The controller is further configured to adjust an output of the UV-LED light sources of the exposure module based on a detected result of the sensor.

Abstract: The present application provides a fingerprint image processing method, applied in an optical fingerprint identification system of an electronic device. The electronic device comprises a display pixel array. The optical fingerprint identification system comprises an image sensing array. The image sensing array is disposed under the display pixel array. The fingerprint image processing method comprises obtaining a background image and obtaining at least an interfering frequency when the display panel is not pressed by a finger of a user; receiving a received image when the display panel is pressed by the finger of the user; performing a subtracting operation on the received image and the background image to obtain a difference image; and performing a filtering operation on the difference image at the at least an interfering frequency to obtain an operational result.

Abstract: An electronic device is provided. The An electronic device comprises a near field communication (NFC) circuit for transmitting a set of near field communication differential signals including a first differential signal and a second differential signal; a housing including a conducting portion with a ground point, a first side and a second side opposite to the first side; and two conductive arms. A current loop is formed by the conductive arm and the conducting portion, and a potential of the ground point is equal to a median potential of the current loop.