Patents by Inventor Te S. Lin
Te S. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9196491Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: GrantFiled: October 22, 2013Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Publication number: 20140106479Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: ApplicationFiled: October 22, 2013Publication date: April 17, 2014Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Patent number: 8563410Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: GrantFiled: November 25, 2009Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Patent number: 8404546Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.Type: GrantFiled: October 14, 2010Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin
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Patent number: 8212253Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.Type: GrantFiled: September 8, 2011Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Publication number: 20110316079Abstract: A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.Type: ApplicationFiled: September 8, 2011Publication date: December 29, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Patent number: 8039375Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.Type: GrantFiled: May 21, 2007Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Publication number: 20110124134Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.Type: ApplicationFiled: November 25, 2009Publication date: May 26, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Te S. Lin, Meng Jun Wang, Ya Hui Chang, Hui Ouyang
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Publication number: 20110059407Abstract: A method of lithography patterning includes forming a first resist pattern over a substrate, baking the first resist features, hardening the first resist features, forming a second resist layer within the hardened first resist features, and patterning the second resist layer to form at least one second resist feature between the hardened first features.Type: ApplicationFiled: August 30, 2010Publication date: March 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Te S. LIN, Yen-Shuo SU, Hsueh-Chang SUNG, Feng-Cheng HSU, Chun Hsiung TSAI, Shiang-Bau WANG, Chun-Kuang CHEN
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Publication number: 20110027955Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin
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Patent number: 7838887Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.Type: GrantFiled: April 30, 2008Date of Patent: November 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin
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Patent number: 7816217Abstract: A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.Type: GrantFiled: December 22, 2005Date of Patent: October 19, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Pang-Yen Tsai, Chih-Chien Chang, Tze-Liang Lee
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Publication number: 20090273034Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventors: Wei-Yen Woon, Chun-Feng Nieh, Ching-Yi Chen, Hsun Chang, Chung-Ru Yang, Li-Te S. Lin
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Patent number: 7612389Abstract: MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.Type: GrantFiled: September 15, 2005Date of Patent: November 3, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Chih-Chien Chang, Tze-Liang Lee
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Patent number: 7494884Abstract: MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.Type: GrantFiled: October 5, 2006Date of Patent: February 24, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Hsin Lin, Li-Te S. Lin, Tze-Liang Lee, Ming-Hua Yu
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Publication number: 20080293204Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.Type: ApplicationFiled: May 21, 2007Publication date: November 27, 2008Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
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Publication number: 20080083948Abstract: MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.Type: ApplicationFiled: October 5, 2006Publication date: April 10, 2008Inventors: Hsien-Hsin Lin, Li-Te S. Lin, Tze-Liang Lee, Ming-Hua Yu
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Patent number: 7307009Abstract: A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.Type: GrantFiled: November 29, 2004Date of Patent: December 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Fang-Cheng Chen, Huin-Jer Lin, Yuan-Hung Chiu, Hun-Jan Tao
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Patent number: 7179715Abstract: The formation of gate spacers on the sides of a gate structure on a semiconductor substrate is provided. In one embodiment, a gate structure is formed on a gate insulator layer of the semiconductor substrate. A liner layer is formed over the exposed surfaces of the substrate, the gate insulator layer, and the gate structure. A layer of gate spacer material is formed over the liner layer. Thereafter, gate spacers are formed from the layer of gate spacer material. A protection layer is formed over portions of the liner layer, gate structure, and the gate spacers. The protection layer is etched back. A first wet etch procedure is performed to remove exposed portions of the liner layer. The protection layer is removed and a second wet etch procedure is performed to remove substantially a top portion and a bottom portion of the liner layer.Type: GrantFiled: March 22, 2005Date of Patent: February 20, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Chien Chiang, Shu-Huei Sun, Li-Te S. Lin
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Patent number: 6864174Abstract: A method for compensating for CD variations across a semiconductor process wafer surface in a plasma etching process including providing a semiconductor wafer having a process surface including photolithographically developed features imaged from a photomask; determining a first dimensional variation of the features with respect to corresponding photomask dimensions along at least one wafer surface direction to determine a first levelness of the process surface; determining gas flow parameters in a plasma reactor for a plasma etching process required to approach a level process surface by reference to an archive of previous plasma etching process parameters carried out in the plasma reactor; carrying out the plasma etching process in the plasma rector according to the determined gas flow parameters; and, determining a second dimensional variation of the features along the at least one wafer surface direction to determine a second levelness of the process surface.Type: GrantFiled: March 20, 2003Date of Patent: March 8, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Te S. Lin, Yui Wang, Ming-Ching Chang, Li-Shung Chen, Huain-Jelin Lin, Yuan-Hong Chin, Hong-Yuan Tao