Patents by Inventor Te Wu

Te Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155808
    Abstract: A two-phase immersion-cooling heat-dissipation composite structure is provided. The heat-dissipation composite structure includes a heat dissipation base, a plurality of high-thermal-conductivity fins, and at least one high-porosity solid structure. The heat dissipation base has a first surface and a second surface that face away from each other. The second surface of the heat dissipation base is in contact with a heating element immersed in a two-phase coolant. The first surface of the heat dissipation base is connected to the high-thermal-conductivity fins. The at least one high-porosity solid structure is located at the first surface of the heat dissipation base, and is connected and alternately arranged between side walls of two adjacent ones of the high-thermal-conductivity fins. Each of the high-porosity solid structure includes a plurality of closed holes and a plurality of open holes.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240155807
    Abstract: A two-phase immersion-type heat dissipation structure having acute-angle notched structures is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins has first and second surfaces defined thereon and connected to each other. An angle between the first surface and the fin surface is from 80 degrees to 100 degrees, and an angle between the second surface and the fin surface is less than 75 degrees.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240155809
    Abstract: A two-phase immersion-type heat dissipation structure having fins for facilitating bubble generation is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fin surface is connected with the plurality of fins. More than half of the fins are functional fins, and at least one side surface of each of the functional fins and the fin surface have an included angle therebetween that is from 80 degrees to 100 degrees. A center line average roughness (Ra) of the side surface is less than 3 ?m, and a ten-point average roughness (Rz) of the side surface is not less than 12 ?m.
    Type: Application
    Filed: November 6, 2022
    Publication date: May 9, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240142180
    Abstract: A two-phase immersion-type heat dissipation structure is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate and a plurality of non-vertical fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other. The non-fin surface is configured to be in contact with a heating element immersed in a two-phase coolant. The fin surface is connected with the non-vertical fins, a cross-sectional contour of one of the non-vertical fins has a top end point and a bottom end point connected with the fin surface, and the top and bottom end points are opposite to each other. A length of a cross-sectional contour line defined from the top end point to the bottom end point is greater than a perpendicular line length of a perpendicular line defined from the top end point to the fin surface.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventors: CHING-MING YANG, CHUN-TE WU, TZE-YANG YEH
  • Publication number: 20240142181
    Abstract: A two-phase immersion-type heat dissipation structure having skived fin with high porosity is provided. The two-phase immersion-type heat dissipation structure having skived fin with high porosity includes a porous heat dissipation structure having a total porosity that is equal to or greater than 5%. The porous heat dissipation structure includes a porous substrate and a plurality of porous and skived fins. The porous substrate has a first surface and a second surface that face away from each other. The second surface of the porous substrate is configured to be in contact with a heating element that is immersed in a two-phase coolant. The plurality of porous and skived fins are integrally formed on the first surface of the porous substrate by skiving. A first porosity of the plurality of porous and skived fins is greater than a second porosity of the porous substrate.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Inventors: CHUN-TE WU, CHING-MING YANG, YU-WEI CHIU, TZE-YANG YEH
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240147662
    Abstract: A two-phase immersion-type heat dissipation structure having a porous structure is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, a plurality of fins, and a reinforcement frame. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other, the non-fin surface is configured to be in contact with a heat source immersed in a two-phase coolant, and the fins are integrally formed on the fin surface. A porous structure is covered onto at least one portion of the fin surface and at least one portion of the plurality of fins, and has a porosity of from 10% to 50% and a thickness that is from 0.1 mm to 1 mm. The reinforcement frame is bonded to the heat dissipation substrate and surrounds another one portion of the plurality of fins.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventors: CHING-MING YANG, CHUN-TE WU, TZE-YANG YEH
  • Patent number: 11968840
    Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240125776
    Abstract: Provided herein are encoded microcarriers for analyte detection in multiplex assays. The microcarriers are encoded with an analog code for identification and comprise a capture agent for analyte detection and a substantially transparent magnetic polymer. The analog code is generated by a two-dimensional shape of a substantially non-transparent layer. Also provided are methods of making the encoded microcarriers disclosed herein. Further provided are methods and kits for conducting a multiplex assay using the microcarriers described herein.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 18, 2024
    Applicant: Plexbio Co., Ltd.
    Inventors: Dean TSAO, Chin-Shiou HUANG, Cheng-Tse LIN, Chien-Te WU, FengKan LU
  • Publication number: 20240128955
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.
    Type: Application
    Filed: April 24, 2023
    Publication date: April 18, 2024
    Inventors: Shao-Yu Steve Wang, Chien-Te Wu, Shang-Chih Hsieh, Nick Tsai
  • Publication number: 20240102741
    Abstract: A heat dissipation structure having a heat pipe is provided. The heat dissipation structure includes a heat dissipation base, a plurality of fins, at least one heat pipe, and at least a first heat dissipation contact material and a second heat dissipation contact material that are different from one another. The heat dissipation base has a first and a second heat dissipation surface opposite to each other. The second heat dissipation surface is connected to the fins. At least one recessed trough is concavely formed on the first heat dissipation surface. The at least one heat pipe is located in the at least one recessed trough. The first and the second heat dissipation contact material are filled in the at least one recessed trough. A melting point of the second heat dissipation contact material is smaller than a melting point of the first heat dissipation contact material.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: CHING-MING YANG, CHUN-TE WU, TZE-YANG YEH
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11935935
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Kun Dai, Wei-Gang Chiu, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin
  • Patent number: 11935349
    Abstract: Techniques for managing access to a physical area are provided. In one technique, first data is extracted from a digital file. Based on identification data within the first data, a database is searched. A data item in the database is identified that matches the identification data. The first data is associated with the data item. After associating the first data with the data item, code data is generated. Encoded data that encodes the code data is then generated. The encoded data is sent over a computer network to a mobile device, or an account, of a user that is associated with the data item.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 19, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Candice Lin, Te-Yu Chu, Phuc Nguyen, Yuwen Wu, Kaoru Watanabe, Shun Tanaka, Jayasimha Nuggehalli
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240085125
    Abstract: An immersion-type heat dissipation structure having high density heat dissipation fins is provided, which includes a heat dissipation substrate and the plurality of sheet-like heat dissipation fins. A thickness of the heat dissipation substrate is from 2 mm to 6 mm, and a bottom surface of the heat dissipation substrate contacts a heating element immersed in a two-phase coolant. The sheet-like heat dissipation fins are integrally formed on an upper surface of the heat dissipation substrate and arranged in high density. A length, a width, and a height of at least one of the sheet-like heat dissipation fins are from 60 mm to 120 mm, from 0.1 mm to 0.5 mm, and from 3 mm to 10 mm, respectively. Further, a distance between at least two of the sheet-like heat dissipation fins that are arranged in parallel to each other is from 0.1 mm to 0.5 mm.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: TZE-YANG YEH, CHING-MING YANG, CHUN-TE WU
  • Publication number: 20240090173
    Abstract: A two-phase immersion-type heat dissipation structure having high density heat dissipation fins is provided. The two-phase immersion-type heat dissipation structure having high density heat dissipation fins includes a heat dissipation substrate, a plurality of sheet-like heat dissipation fins, and a reinforcement structure. A bottom surface of the heat dissipation substrate is in contact with a heating element immersed in a two-phase coolant. The plurality of sheet-like heat dissipation fins are integrally formed on an upper surface of the heat dissipation substrate and arranged in high density. An angle between at least one of the sheet-like heat dissipation fins and the upper surface of the heat dissipation substrate is from 60° to 120°. At least one of the sheet-like heat dissipation fins has a length from 50 mm to 120 mm, a width from 0.1 mm to 0.35 mm, and a height from 2 mm to 8 mm.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: TZE-YANG YEH, CHING-MING YANG, CHUN-TE WU
  • Patent number: 11927303
    Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 12, 2024
    Assignee: HTC Corporation
    Inventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
  • Publication number: 20240079497
    Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Huang, Gao-Ming Wu, Katherine H CHIANG, Chung-Te Lin
  • Patent number: D1024460
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: April 23, 2024
    Assignee: PLANDDO CO., LTD.
    Inventors: Tsung-Te Sun, Chao-Shun Liang, Chia-Hsin Wu, Ping-Yun Su, Yu-Huai Yang