Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.

Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Abstract: A heat dissipation unit includes a main body having a first and a second plate member, which are closed to each other to together define an airtight chamber in between them. A working fluid is filled in the airtight chamber. A first wick structure layer and a holding-down member are provided between the first and the second plate member and received in the airtight chamber. The holding-down member is located above the first wick structure layer, such that the first wick structure layer is held down by the holding-down member to be closely and flatly attached to the second plate member without warping.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: A two-phase immersion-type heat dissipation structure having skived fins is provided. The two-phase immersion-type heat dissipation structure includes an upper cover structure, a lower cover structure, the plurality of skived fins, and a reinforcement frame. The skived fins are integrally formed on an upper surface of the upper cover structure by a skiving process. A bottom surface of the upper cover structure has an upper sintering structure formed thereon, and an upper surface of the lower cover structure has a lower sintering structure formed thereon. A bottom surface of the lower cover structure contacts a heating element immersed in a two-phase coolant. The lower cover structure is correspondingly bonded to the upper cover structure. An inner chamber that is vacuum-sealed is formed between the bottom surface of the upper cover structure and the upper surface of the lower cover structure, and contains liquid therein.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.

Abstract: The invention discloses a target tracking method applied to a video transmission, which can automatically track a specific target and capture images according to sound. The target tracking method includes the following steps: step one is to set a first target area; step two is to determine whether a corresponding sound source position points to the first target area according to a sound source position signal; step three is to capture an image of the first target area and output to a display unit by a camera unit when the sound source position points to the first target area; and step four is to execute a sound source tracking procedure when the sound source position is not pointing to the first target area.

Abstract: A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.

Abstract: A two-phase immersion-type heat dissipation structure having fins with different thermal conductivities is provided. The two-phase immersion-type heat dissipation structure includes a heat dissipation substrate, and a plurality of fins. The heat dissipation substrate has a fin surface and a non-fin surface that face away from each other. The non-fin surface is configured to be in contact with a heating element immersed in a two-phase coolant. The fin surface is connected with the plurality of fins. At least one of the plurality of fins is a functional fin that is made of a single metal material and has two or more thermal conductivities. A thermal conductivity of a lower portion of the functional fin that is connected with the heat dissipation substrate is lower than thermal conductivities of other portions of the functional fin.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.

Abstract: A brain tumor types distinguish system includes an image outputting device and a server computing device. The image outputting device outputs at least three brain images captured from the position of a brain tumor. The server computing device pre-stores a plurality of distinguish pathways corresponding to different types of brain tumors. The server computing device includes an image receiving module, an image pre-processing module, a data comparison module and a distinguish module. The image receiving module receives the brain images. The image pre-processing module pre-processes the brain images to obtain corresponding processed images thereof. The data comparison module compares the brain images and the processed images with the distinguish pathways to obtain at least three comparison results. The distinguish module statistically analyzes the comparison results to obtain a distinguish result.

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A method of preparation of a ceramic slurry for use in 3D printing includes steps of: (A) providing a plasticizer and a disperser and mixing the plasticizer and the disperser evenly; (B) mixing the mixture obtained in step (A) with an adhesive, wherein the adhesive is polyvinyl alcohol; and (C) adding a Yttria-stabilized zirconia powder to the mixture obtained in step (B) to produce, by sufficient blending and deaerating, the ceramic slurry for use in 3D printing. A method of preparation of a ceramic product includes steps of: (A) preparing a ceramic slurry with the method; (B) performing 3D printing with the ceramic slurry to form a primary green body; (C) placing the primary green body in a freezer to undergo a refrigeration process, thereby causing crystallization of polyvinyl alcohol; and (D) thawing the frozen primary green body to form a plastic green body with gel structure.

Abstract: A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.

Abstract: The present invention discloses a Polymerase Chain Reaction (PCR) apparatus for real-time detecting of one or more fluorescent signals. According to the apparatus, the PCR is performed by controlling heating and cooling intervals of a reagent container receiving space. With the aid of an added specific probe and fluorescent material, as well as a light source and a spectrometer, a generated fluorescent signal is detected. Meanwhile, the apparatus is also pre-loaded with an algorithm configured to analyze and quantify the fluorescent signal in a real-time manner.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.