Patents by Inventor Te Yin

Te Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7638157
    Abstract: A method of fabricating an electrode assembly of a sensor is described. The sensor has a field effect transistor. The electrode assembly is separated from the field effect transistor by only a conductive line. The sensor is functioned to detect different glucose concentrations. A solid layer of tin oxide is deposited on a substrate board. A ?-D-glucose oxidase and polyvinyl alcohol bearing styrylpyridinium groups are placed in 100 ?l of sulfuric acid, to form an enzyme mixture. The enzyme mixture is dropped on the solid layer of tin oxide. The enzyme mixture is dried. The enzyme mixture is exposed to a UV ray. The enzyme mixture is dried and stabilized. The enzyme mixture is immersed in a sulfuric buffer.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: December 29, 2009
    Assignee: Chung Yuan Christian University
    Inventors: Shen-Kan Hsiung, Jung-Chuan Chou, Tai-Ping Sun, Wen-Yaw Chung, Li-Te Yin, Chung-We Pan
  • Patent number: 7633109
    Abstract: A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: December 15, 2009
    Assignee: Nanya Technology Corp.
    Inventors: Tzung-Han Lee, Chih-Hao Cheng, Te-Yin Chen, Chung-Yuan Lee, En-Jui Li
  • Publication number: 20090148993
    Abstract: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.
    Type: Application
    Filed: March 25, 2008
    Publication date: June 11, 2009
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-An Yu, Te-Yin Chen, Hai-Han Hung
  • Patent number: 7521741
    Abstract: A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 ?m. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: April 21, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Jong, Ruey-Hsin Liu, Yueh-Chiou Lin, Shun-Liang Hsu, Chi-Hsuen Chang, Te-Yin Hsia
  • Publication number: 20090008691
    Abstract: A DRAM structure has a substrate, a buried transistor with a fin structure, a trench capacitor, and a surface strap on the surface of the substrate. The surface strap is used to electrically connect a drain region to the trench capacitor.
    Type: Application
    Filed: December 28, 2007
    Publication date: January 8, 2009
    Inventors: Tzung-Han Lee, Chih-Hao Cheng, Te-Yin Chen, Chung-Yuan Lee, En-Jui Li
  • Publication number: 20080318377
    Abstract: Method for fabricating a self-aligned gate of a transistor including: forming a plurality of deep trench capacitors in a substrate, concurrently forming a surface strap and a contact pad on a surface of the substrate, wherein a spacing between the surface strap and the contact pad exposes a portion of an active area, filling the spacing with a dielectric layer, forming a photoresist pattern on the substrate, wherein the photoresist has an opening situated directly above the spacing between the surface strap and the contact pad, etching away the dielectric layer and a portion of a shallow trench isolation region through the opening thereby forming an upwardly protruding fin-typed channel structure, forming a gate dielectric layer on the upwardly protruding fin-typed channel structure, and forming a gate on the gate dielectric layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: December 25, 2008
    Inventors: Tzung-Han Lee, Chih-Hao Cheng, Pei-Tzu Lee, Te-Yin Chen, Chung-Yuan Lee
  • Publication number: 20080277709
    Abstract: A DRAM structure includes a substrate, a MOS transistor, a deep trench capacitor, a surface strap positioned on the surface of the substrate and interconnecting a drain of the MOS transistor and an electrode of the deep trench capacitor, wherein the sidewall and the top surface of the surface strap are covered with an insulating layer. A passing gate is positioned on the insulating layer.
    Type: Application
    Filed: October 14, 2007
    Publication date: November 13, 2008
    Inventors: Tzung-Han Lee, Chih-Hao Cheng, Te-Yin Chen, Chung-Yuan Lee
  • Publication number: 20080001189
    Abstract: A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 ?m. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
    Type: Application
    Filed: November 6, 2006
    Publication date: January 3, 2008
    Inventors: Yu-Chang Jong, Ruey-Hsin Liu, Yueh-Chiou Lin, Shun-Liang Hsu, Chi-Hsuen Chang, Te-Yin Hsia
  • Publication number: 20070267693
    Abstract: A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 22, 2007
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsing-Yi Chien, Yu-Chang Jong, Ruey-Hsin Liu, Te-Yin Hsia
  • Publication number: 20070081809
    Abstract: An automatic focusing camera base has a seat, a motor, a focusing device, a contact set, and a transmission device. The motor is mounted on the seat and has a shaft. The focusing device is mounted on the seat, which can move relative to the seat. The contact set is mounted on the seat, connected to the motor and a detecting circuit for the zero adjustment of the focusing device and has a first conductive member connected to the shaft and a second conductive member. The transmission device is mounted between the motor and the focusing device and has an active member selectively contacts the second conductive member. The active member and the motor are responsible for driving the focusing device and activating the detecting circuit without a ray-emitter and a ray-interceptor. The structure of the automatic focusing camera base is simple and compact.
    Type: Application
    Filed: July 11, 2006
    Publication date: April 12, 2007
    Inventor: Te-An Yin
  • Publication number: 20070081093
    Abstract: An automatic focusing camera base has a seat, a motor, a focusing device and a transmission device. The motor is mounted and horizontally lies on the seat and has a shaft. The focusing device is mounted on the seat and can move relative to the seat. The transmission device is mounted between the motor and the focusing device and has an active member mounted around the shaft and being movable along the shaft and a passive member mounted pivotally on the seat, abutting and driven by the active member to pivot and move the focusing device. The transmission device are designed especially to cooperate with and allow the motor to horizontally lie on the seat instead of upright standing and therefore a thickness of the automatic focusing camera base along a linear line perpendicular to an axis of the motor is reduced.
    Type: Application
    Filed: July 14, 2006
    Publication date: April 12, 2007
    Applicant: INCHAN TECHNOLOGY CO., LTD.
    Inventor: Te-An YIN
  • Publication number: 20070023286
    Abstract: A method of fabricating an electrode assembly of a sensor is described. The sensor has a field effect transistor. The electrode assembly is separated from the field effect transistor by only a conductive line. The sensor is functioned to detect different glucose concentrations. A solid layer of tin oxide is deposited on a substrate board. A ?-D-glucose oxidase and polyvinylalchol bearing styrylpyridinium groups are placed in 100 ?l of sulfuric acid, to form an enzyme mixture. The enzyme mixture is dropped on the solid layer of tin oxide. The enzyme mixture is dried. The enzyme mixture is exposed to a UV ray. The enzyme mixture is dried and stabilized. The enzyme mixture is immersed in a sulfuric buffer.
    Type: Application
    Filed: September 19, 2006
    Publication date: February 1, 2007
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Shen-Kan Hsiung, Jung-Chuan Chou, Tai-Ping Sun, Wen-Yaw Chung, Li-Te Yin, Chung-We Pan
  • Publication number: 20060222355
    Abstract: An auto-focusing camera has a base, a focusing element, a lens, a motor and a transmission assembly. The focusing element is mounted movably on the base. The lens is mounted on the focusing element. The motor is mounted and lies flatly on the base and has a shaft mounted rotatably to the motor. The transmission assembly connects to the shaft on the motor and the focusing element and allows the motor to move the focusing element through the transmission assembly. The motor lying on the base decreases a thickness of the auto-focusing camera along an axis of the lens and makes the auto-focusing camera thin and compact. The electrical appliance with the auto-focusing camera is thin, compact and salable.
    Type: Application
    Filed: March 27, 2006
    Publication date: October 5, 2006
    Applicant: Inchan Technology Co., Ltd.
    Inventor: Te-An Yin
  • Publication number: 20050106607
    Abstract: This invention is provided a biochip containing splitable reaction wells and method for producing same and application thereof. The invention avoids cross contamination or interference between different samples on the same biochip. In addition, the soft polymer film removed from reaction wells may be reused on different substrates, thereby saving the cost of experiment or clinical testing.
    Type: Application
    Filed: October 18, 2004
    Publication date: May 19, 2005
    Applicants: Industrial Technology Research Institute, Co-Wealth Medical Science & Biotechnology INC.
    Inventors: Li-Te Yin, Chih-Yu Hu, Chao-Yun Tsao, Su-Fung Chiou, Jia-Huey Tsao
  • Publication number: 20050106649
    Abstract: Polyallylamine conjugates and applications thereof for biological signal amplification are provided by utilizing the essential amino group of polyallylamine to covalently bind with capture agents and signal molecules having the functional groups selected from a group consisting of —NHS, —CO, —S?O2 and —C?O—C?O. The resulting conjugates having more than one signaling entities can be further implemented for biological expression with enhancing effect on biological signal intensity, such that the sensitivity of detection for the variation between biological interactions is largely increased.
    Type: Application
    Filed: October 15, 2004
    Publication date: May 19, 2005
    Applicants: Industrial Technology Research Institute, Co-Wealth Medical Science & Biotechnology INC.
    Inventors: Chao-Yun Tsao, Li-Te Yin, Su-Fung Chiou, Chung-We Pan, Jia-Huey Tsao
  • Publication number: 20050100969
    Abstract: The present invention provides a substrate for protein microarrays, whereby compound A and GPTS are mixed for coating onto a solid support to form a layer, wherein said compound A is selected from a group consisting of nitrocellulose, poly(styrene-co-maleic anhydride) and polyvinylidene fluoride. Moreover, the present invention also provides a protein microarray by depositing proteins on said layer of said substrate.
    Type: Application
    Filed: October 7, 2004
    Publication date: May 12, 2005
    Applicants: Industrial Technology Research Institute, Co-Wealth Medical Science & Biotechnology INC.
    Inventors: Li-Te Yin, Chao-Yun Tsao, Chung-We Pan, Su-Fung Chiou, Zheng-Cheng Chen
  • Publication number: 20040209383
    Abstract: A protein chip and the preparation thereof. The preparation includes providing a substrate with a positive photoresist thereon, forming a spot array valley in the positive photoresist using a spot pattern mask, forming an adhesive layer on the substrate and filling the spot array valley thereon, performing a full region exposure on the positive photoresist and removing the same, thereby leaving the adhesive layer as a spot array pattern on the substrate, and forming an immobilizing material cover the surface of the spot array pattern to obtain a 3-dimensional structure of the immobilizing material.
    Type: Application
    Filed: April 17, 2003
    Publication date: October 21, 2004
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, CO-WEALTH MEDICAL SCIENCE & BIOTECHNOLOGY, INC.
    Inventors: Li-Te Yin, Jia-Huey Tsao, Chung-We Pan, Zu-Sho Chow, Chao-Yun Tsao
  • Patent number: 6194232
    Abstract: A wafer processing method is provided for processing a plurality of wafer lots concurrently in a plurality of different tanks. Each wafer lot is assigned a specific start number, position number, tank number and wafer number. Upon a wafer completing a process in a tank, a finish signal is generated, and a next wafer lot information for a wafer lot that needs the completed tank for processing is loaded into a memory. Once the tank is free and available, the next wafer from a wafer lot is moved in while all other tanks are being processed independently and concurrently. The wafer lots do not need to queue in sequence for other wafer lots to complete processing in different tanks. Total processing time can therefore be reduced and through-put increased.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: February 27, 2001
    Assignees: ProMos Technology, Inc,, Mosel Vitelic Inc, Siemens AG
    Inventor: Te-Yin Kao
  • Patent number: 5470783
    Abstract: An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: November 28, 1995
    Assignee: AT&T IPM Corp.
    Inventors: Tzu-Yin Chiu, Frank M. Erceg, Te-Yin M. Liu, Kenenth G. Moerschel, Michael A. Prozonic, Janmye Sung
  • Car
    Patent number: D563280
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 4, 2008
    Assignee: Shenyang Brilliance Jinbei Automobile Co., Ltd
    Inventors: Rufei Xing, Dongming Liang, Qiang Liu, Ruifa Zhang, Dong Chen, Yang Mou, Na Chen, Ruisheng Li, Yajuan Li, Zhenghai Lai, Te Yin, Ying Zhang, Lei Zhang, Zhengyu Jia, Hong Zhang, Dacheng Yang, Jin Liu