Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.

Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.

Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.

Abstract: A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: One example of a semiconductor package includes a first die pad, a first die, a second die pad, and a second die. The first die pad includes a main portion and a U-shaped rail portion extending from the main portion. The first die is electrically coupled to the first die pad. The second die pad is proximate the U-shaped rail portion of the first die pad. The second die is electrically coupled to the second die pad. The second die includes a magnetic field sensor.

Abstract: A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.

Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.

Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.

Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.