Patents by Inventor Teck Sim Lee

Teck Sim Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10083899
    Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
  • Patent number: 10037934
    Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
  • Publication number: 20180211907
    Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
  • Publication number: 20180158758
    Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 7, 2018
    Inventors: Ralf OTREMBA, Chooi Mei Chong, Josef Hoeglauer, Teck Sim Lee, Klaus Schiess, Xaver Schloegel
  • Patent number: 9991183
    Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Josef Hoeglauer, Teck Sim Lee, Ralf Otremba, Klaus Schiess, Xaver Schloegel, Juergen Schredl
  • Patent number: 9978671
    Abstract: A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 22, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Fabio Brucchi, Teck Sim Lee, Xaver Schloegel, Franz Stueckler
  • Patent number: 9972576
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Teck Sim Lee, Amirul Afiq Hud, Fabian Schnoy, Felix Grawert, Uwe Kirchner, Bernd Schmoelzer, Franz Stueckler
  • Patent number: 9922910
    Abstract: An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant and being functionalized for promoting heat dissipation via the interface structure on a heat dissipation body.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Murugan, Lee Shuang Wang
  • Publication number: 20180061745
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 1, 2018
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Publication number: 20170179009
    Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 22, 2017
    Inventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler
  • Publication number: 20170148743
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Application
    Filed: November 24, 2016
    Publication date: May 25, 2017
    Inventors: Ralf OTREMBA, Teck Sim LEE, Amirul Afiq HUD, Fabian SCHNOY, Felix GRAWERT, Uwe KIRCHNER, Bernd SCHMOELZER, Franz STUECKLER
  • Publication number: 20170098598
    Abstract: An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant and being functionalized for promoting heat dissipation via the interface structure on a heat dissipation body.
    Type: Application
    Filed: September 21, 2016
    Publication date: April 6, 2017
    Inventors: Ralf OTREMBA, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Nurugan, Lee Shuang Wang
  • Publication number: 20160365296
    Abstract: A device includes an encapsulation material and a first lead and a second lead protruding out of a surface of the encapsulation material. A recess extends into the surface of the encapsulation material. An elevation is arranged on the surface of the encapsulation material. The first lead protrudes out of the elevation.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 15, 2016
    Inventors: Ralf Otremba, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Murugan, Lee Shuang Wang
  • Publication number: 20160233149
    Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.
    Type: Application
    Filed: February 4, 2016
    Publication date: August 11, 2016
    Inventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
  • Patent number: 9373566
    Abstract: In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a control electrode. The electronic component further includes a die pad having a first surface, a plurality of leads and a gull-wing shaped conductive element coupled to a first lead of the plurality of leads. The first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between the control electrode and the first lead.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Teck Sim Lee
  • Patent number: 9324642
    Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Püschner, Bernhard Schätzler, Teck Sim Lee, Franz Gabler, Pei Pei Kong, Boon Huat Lim
  • Publication number: 20160056092
    Abstract: A hybrid leadframe is provided comprising a thin leadframe layer comprising a diepad and a structured region; and a metal layer being thicker than the thin leadframe layer and arranged on the diepad.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 25, 2016
    Inventors: Ralf OTREMBA, Chooi Mei CHONG, Josef HOEGLAUER, Teck Sim LEE, Klaus SCHIESS, Xaver SCHLOEGEL
  • Patent number: 9263563
    Abstract: In an embodiment, a semiconductor device package includes a bidirectional switch circuit. The bidirectional switch circuit includes a first semiconductor transistor mounted on a first die pad, a second semiconductor transistor mounted on a second die pad, the second die pad being separate from the first die pad, and a conductive connector extending between a source electrode of the first transistor and a source electrode of the second transistor.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 16, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Fabio Brucchi, Franz Stückler, Teck Sim Lee
  • Patent number: 9230880
    Abstract: An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 5, 2016
    Assignee: Infineon Technolgies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Teck Sim Lee, Xaver Schloegel, Klaus Schiess
  • Publication number: 20150270208
    Abstract: A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Ralf OTREMBA, Fabio BRUCCHI, Teck Sim LEE, Xaver SCHLOEGEL, Franz STUECKLER