Patents by Inventor Tecla Ghilardi
Tecla Ghilardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955175Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps.Type: GrantFiled: April 26, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventors: Tyler L. Betz, Tecla Ghilardi, Violante Moschiano
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Publication number: 20230413563Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Patent number: 11762767Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or moreType: GrantFiled: April 22, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Giuseppina Puzzilli, Vamsi Pavan Rayaprolu, Ashutosh Malshe, James Fitzpatrick, Shyam Sunder Raghunathan, Violante Moschiano, Tecla Ghilardi
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Patent number: 11751396Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: January 20, 2022Date of Patent: September 5, 2023Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Publication number: 20220375522Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps.Type: ApplicationFiled: April 26, 2022Publication date: November 24, 2022Inventors: Tyler L. Betz, Tecla Ghilardi, Violante Moschiano
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Publication number: 20220342813Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or moreType: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Kishore Kumar Muchherla, Giuseppina Puzzilli, Vamsi Pavan Rayaprolu, Ashutosh Malshe, James Fitzpatrick, Shyam Sunder Raghunathan, Violante Moschiano, Tecla Ghilardi
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Publication number: 20220139958Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: January 20, 2022Publication date: May 5, 2022Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Patent number: 11309039Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.Type: GrantFiled: March 16, 2021Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Patent number: 11264404Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: June 17, 2020Date of Patent: March 1, 2022Assignee: Micron Technology, Inc.Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Publication number: 20210399006Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: June 17, 2020Publication date: December 23, 2021Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
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Publication number: 20210202020Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Patent number: 10950316Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.Type: GrantFiled: August 11, 2020Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Publication number: 20200372961Abstract: Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Patent number: 10777286Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.Type: GrantFiled: February 5, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Publication number: 20200211660Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.Type: ApplicationFiled: February 5, 2019Publication date: July 2, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
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Patent number: 7656712Abstract: A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.Type: GrantFiled: April 16, 2008Date of Patent: February 2, 2010Inventors: Carlo Lisi, Tecla Ghilardi
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Patent number: 7551465Abstract: A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.Type: GrantFiled: April 27, 2007Date of Patent: June 23, 2009Inventors: Tecla Ghilardi, Paolo Tessariol, Giorgio Servalli, Alessandro Grossi, Angelo Visconti, Emilio Camerlenghi
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Publication number: 20080266929Abstract: A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: STMICROELECTRONICS S.r.L.Inventors: Tecla Ghilardi, Paolo Tessariol, Giorgio Servalli, Alessandro Grossi, Angelo Visconti, Emilio Camerlenghi
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Publication number: 20080259683Abstract: A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.Type: ApplicationFiled: April 16, 2008Publication date: October 23, 2008Applicant: STMicroelectronics S.r.l.Inventors: Carlo Lisi, Tecla Ghilardi
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Patent number: 6944061Abstract: The present invention relates to a particular single cell erasing method for recovering memory cells under reading or programming disturbs in non volatile semiconductor memory electronic devices comprising cell matrix split in sectors and organized in rows, or word lines, and columns, or bit lines. This kind of memory devices generally provides the application of a sector erasing algorithm with subsequent testing phase (erase-verify); but the method according to the present invention provides a bit by bit erasing by applying to each single word line a negative voltage used during the erasing of a whole sector and on the drain terminal of each single cell a programming voltage. With this kind of selective bias it is possible to perform a single cell, or bit by bit, erasing, allowing all the cells in case under a reading or programming disturb increasing the original threshold value thereof to be recovered.Type: GrantFiled: November 26, 2003Date of Patent: September 13, 2005Assignee: STMicroelectronics, S.r.l.Inventors: Emilio Camerlenghi, Giovanni Campardo, Tecla Ghilardi